W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 70

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
7.7.1 Clock Control
The Watchdog timeout selection is made using bits WD[1:0] as shown in the Figure below.
period. The Watchdog is clocked directly from the CLK pin. The Watchdog has four timeout
selections based on the input CLK clock frequency as shown in the Figure 7.1. The selections
are a pre-selected number of clocks.
*W7100A clock frequency = 88.4736MHz
enabled, it will activate 512 clocks later regardless of the interrupt. Therefore, the actual
Watchdog timeout is the number of clocks chosen from Watchdog intervals plus 512 clocks
(always CLK pin).
7.8
value to WDCON. TA is an SFR addressed 0xC7.
Clock control register CKCON(0x8E) contains WD[1:0] bits to select Watchdog Timer timeout
Note that the time period shown above is for the interrupt events. When the reset is
Since the WDCON is timed access register, user must use following procedure when set a
MOV TA, #0xAA
MOV TA, #0x55
;Any direct addressing instruction writing timed access register
User always use this sequence every setting the WDCON
7
WD1
Timed Access Registers
6
WD0
Register name
WDCON(0xD8)
WD[1:0]
Figure 7.7 Clock Control register – Watchdog bits
00
01
10
11
5
-
Table 7.5 Timed Access Registers
Table 7.4 Watchdog Intervals
Watchdog Interval
4
-
Watchdog configuration
Description
CKCON (0x8E)
2
2
2
2
17
20
23
26
3
-
2
MD2
Number of Clocks
67108864
1048576
8388608
131072
1
MD1
0
MD0
Ver. 1.12
Reset
0x03
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