W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 37

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
LCD displays, etc. After reset, MD[2:0] will be restored to the default value of 0x07, which
means that slow devices work properly. Users can change the MD[2:0] value to speed up/slow
down the software execution. The value of MD[2:0] can be changed any time during program
execution (e.g. between MOVX and different speed devices).
clock cycle.
2.5.6 Internal Memory Wait States Register
internal 64KB RAM, TCPIPCore and 255Byte internal flash.
This read/write pulse width must have a minimum of 3 clock cycle and a maximum of 8
Internal Memory Wait States Register INTWTST(0x9C) is used for setting the access time of
-
-
-
Internal ram WTST value means below access time in table 2.3.
TCPIPCore, Internal flash WTST value means below access time in table 2.4.
7
Ram WTST
Ram WTST: Set the 64Kbytes RAM access time, has two 2bit value 0 ~ 3.
TCPIPCore WTST: Set the TCPIPCore access time, has 3bit value 0 ~ 7.
Flash WTST: Set the internal flash access time, has 3bit value 0 ~ 7.
6
Figure 2.24 Internal Memory Wait States Register
Table 2.6 TCPIPCore / Flash WTST Bit Values
MD[2:0]
WTST
5
…
7
2
1
0
3
2
1
0
TCPIPCore WTST
Table 2.4 MD[2:0] Bit Values
Table 2.5 Ram WTST Bit Values
4
INTWTST (0x9C)
3
Pulse Width[clock]
Pulse Width[clock]
Not Used
Not Used
2
…
8
3
5
4
3
2
Flash WTST
1
Ver. 1.12
0
Reset
0xFF
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