W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 51

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
facilitate pulse width measurements.
5.1.2 Interrupts
register, and priorities can be configured in the IP register.
External input pins, GATE0 and GATE1, can be programmed to function as a gate to
Timer0, 1 interrupt related bits are shown below. An interrupt can be toggled by the IE
GATE
TF1
EA
7
7
Note: EA - Enable global interrupts
7
Note: GATE - Gating control
Note: TR0 - Timer0 run control bit
TR1
CT - Counter or timer select bit
M1, M0 – Mode select bits
TR1 - Timer 1 run control bit
CT
ET0 - Enable Timer0 interrupts
ET1- Enable Timer1 interrupts
6
6
6
-
Timer1
1: Counter mode, Timer x clock source from Tx pin
0: Timer mode, internally clocked
1: Timer x is enabled while GATEx pin is at high and TRx control b
it is set
0: Timer x is enabled while TRx control bit is set
1: Enabled
0: Disabled
1: Enabled
0: Disabled
Figure 5.1 Timer0, 1 Control Mode Register
Figure 5.2 Timer0, 1 Configuration Register
TF0
M1
ET2
5
5
5
Figure 5.3 Interrupt Enable Register
TR0
M0
4
4
ES
4
TMOD (0x89)
IE (0xA8)
TCON (0x88)
GATE
IE1
ET1
3
3
3
IT1
CT
EX1
2
2
2
Timer0
IE0
M1
ET0
1
1
1
Ver. 1.12
IT0
M0
EX0
0
0
0
Reset
Reset
Reset
0x00
0x00
0x00
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