W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 6

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
List of Figures
Figure 1.1 W7100A Block Diagram ....................................................................... 12
Figure 1.2 Accumulator A Register ....................................................................... 13
Figure 1.3 B Register ....................................................................................... 13
Figure 1.4 Program Status Word Register ............................................................... 13
Figure 1.5 PSW Register ................................................................................... 13
Figure 1.6 TCPIPCore Block Diagram .................................................................... 14
Figure 1.7 W7100A Pin Layout ............................................................................ 16
Figure 1.8 W7100A QFN 64 Pin Layout ................................................................... 17
Figure 1.9 Power Design ................................................................................... 24
Figure 2.1 Code / Data Memory Connections .......................................................... 26
Figure 2.2. Boot Sequence Flowchart ................................................................... 27
Figure 2.3 APP Entry Process .............................................................................. 27
Figure 2.4 Changing the code memory Status at RB = ‘0’ ........................................... 28
Figure 2.5 Data Memory Map ............................................................................. 29
Figure 2.6 Standard 8051 External Pin Access Mode (EM[2:0] = “001”) ............................ 30
Figure 2.7 Standard 8051 External Pin Access Mode (EM[2:0] = “011”) ............................ 30
Figure 2.8 Direct 8051 External Pin Access Mode (EM[2:0] = “101”) ............................... 31
Figure 2.9 Direct 8051 External Pin Access Mode (EM[2:0] = “111”) ............................... 31
Figure 2.10 Internal Memory Map ........................................................................ 32
Figure 2.11 SFR Memory Map ............................................................................. 32
Figure 2.13 PWE bit of PCON Register ................................................................... 33
Figure 2.14 Code memory Wait States Register ........................................................ 33
Figure 2.12 Waveform for code memory Synchronous Read Cycle with Minimal Wait States
Figure 2.13 Waveform for code memory Synchronous Write Cycle with Minimal Wait
Figure 2.17 Data Pointer Extended Register ............................................................ 35
Figure 2.18 Data Pointer Extended Register ............................................................ 35
Figure 2.19 MOVX @RI Extended Register ............................................................... 35
Figure 2.20 Data Pointer Register DPTR0 ............................................................... 35
Figure 2.21 Data Pointer 1 Register DPTR1 ............................................................. 35
Figure 2.22 Data Pointer Select Register ............................................................... 36
Figure 2.23 Clock Control Register – STRETCH bits .................................................... 36
Figure 2.24 Internal Memory Wait States Register .................................................... 37
Figure 2.25 Internal Memory Wait States Register .................................................... 38
Figure 2.26 First Byte of Internal Memory Wait States Register .................................... 38
(WTST = ‘3’) ................................................................................. 34
States(WTST = ‘3’) .......................................................................... 34
Ver. 1.12
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