W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 52

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
result by hardware. That is, interrupts can be generated or cancelled by software.
5.1.3 Timer0 – Mode0
counts (valid bits) roll over from 1 to 0, Timer0 interrupt flag TF0 is set. The timer starts
counting when TCON.4 =1 and either TMOD.3 = 0 or GATE0 = 1. By setting TMOD.3 = 1, the
external input GATE0 can control Timer0 to manage the pulse width measurements. The 13-
bit register consists of 8 bits TH0 and 5 bits of TL0. The upper 3 bits of TL0 should be ignored.
Refer to the following Figure for details.
All of the bits which generate interrupts can be set or cleared by software, with the same
The Timer0 register is configured as a 13-bit register (8bit: Timer, 5bit: prescaler). As the all
Interrupt
TF1
7
Note: PT0 - Enable global interrupts
7
Flag
-
TF0
TF1
Note: TF0 - Timer0 interrupt (overflow) flag. Automatically cleared when proce
TR1
TF1 - Timer1 interrupt (overflow) flag. Automatically cleared when proces
PT1 - Enable Timer0 interrupts
Unimplemented bit - Read as 0 or 1
6
Internal, Timer0
Internal, Timer1
6
-
Function
ssor branches to interrupt routine
sor branches to interrupt routine
Figure 5.5 Timer0, 1 Configuration Register
TF0
PT2
5
5
Figure 5.4 Interrupt Priority Register
Table 5.3 Timer0, 1 interrupts
TR0
Level/Edge
PS
4
4
Active
-
-
IP (0xB8)
TCON (0x88)
IE1
PT1
3
3
Flag Resets
Hardware
Hardware
IT1
PX1
2
2
Vector
IE0
PT0
0x0B
0x1B
1
1
Natural Priority
Ver. 1.12
IT0
PX0
0
0
2
4
Reset
Reset
0x00
0x00
52