W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 38

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
2.5.7 Address Latch Enable Register
(Address Latch Enable) signal can be controlled by ALECON SFR.
ALE signal maintains 1+n clock and down to ‘0’.
The initial value of ALECON is 0xFF. User can configure this value depending on external
device speed.
2.5.8 External Memory Wait States Register
of this SFR user can control the value from 0 to 65535.
ALECON SFR is used for standard 8051 external pin access mode. The time duration of ALE
If we set the ALECON to 1, ALE signal will be down to ‘0’ after 1 clock. If we set it to ‘n’,
ALE maintain duration = ALECON value + 1 clock
EXTWTST SFR is used for configuring the timing of external memory access. Using the 16bit
EW.15
EW.7
AC.7
7
7
7
Figure 2.27 Second Byte of Internal Memory Wait States Register
EW.14
Figure 2.26 First Byte of Internal Memory Wait States Register
EW.6
AC.6
6
6
6
Figure 2.25 Internal Memory Wait States Register
EW.13
EW.5
WTST
AC.5
5
5
5
7
6
5
4
3
2
1
0
EW.12
EW.4
AC.4
4
4
4
EXTWTST0 (0x9D)
EXTWTST1 (0x9E)
ALECON (0x9F)
EW.11
EW.3
AC.3
3
3
3
Pulse Width[clock]
EW.2
EW.10
AC.2
2
2
2
10
9
8
7
6
5
4
3
EW.1
EW.9
AC.1
1
1
1
EW.0
EW.8
AC.0
Ver. 1.12
0
0
0
Reset
Reset
Reset
0xFF
0xFF
0xFF
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