W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 33

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
2.5
information about peripheral SFR, please refer to the section 2.5.11 ‘Peripheral SFR’.
2.5.1 Program Code Memory Write Enable Bit
Program Write signal activity during MOVX instructions.
the accumulator register into the code memory addressed by using the DPTR register (active
DPH:DPL)
memory addressed by using the P2 register (bits 15:8) and Rx register (bits 7:0).
2.5.2 Program Code Memory Wait States Register
The following section describes SFR of W7100A and its functions. For more detailed
Inside the PCON register, the Program Write Enable (PWE) bit is used to enable/disable
When the PWE bit is set to logic ‘1', the “MOVX @DPTR, A” instruction writes the data from
Note: 1.
Wait states register provides the information for code memory access time.
Note: 1. These bits are considered during program fetches and MOVC instructions only.
The “MOVX @Rx, A” instruction writes the data from the accumulator register into code
SMOD0
7
-
7
2. Read cycle takes minimal 4 clock period and maximal 8 clock periods.
SFR definition
Since code memory write are performed by MOVX instruction, CKCON
register regulates the CODE-WR pulse width.
PCON.2 ~ PCON.0 bits are reserved. They must be set to ‘0’
6
-
6
-
WTST[2:0]
Figure 2.14 Code memory Wait States Register
7
6
5
4
3
2
5
-
5
-
Figure 2.13 PWE bit of PCON Register
Table 2.2 WTST Register Values
PWE
4
-
4
PCON (0x87)
WTST (0x92)
3
-
3
-
Access Time [clk]
WTST.2
Not Used
2
2
0
8
7
6
5
4
WTST.1
1
1
0
WTST.0
Ver. 1.12
0
0
0
Reset
Reset
0x00
0x07
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