W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 35

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
2.5.3 Data Pointer Extended Registers
memory addresses when accessing to data located above 64KB. After reset, DPX0, DPX1, and
MXAX restores to the default value 0x00.
A[23:16] is always equal to the content of DPX0(0x93)/DPX1(0x95). When MOVX instruction
uses R0 or R1 register, the most significant part of the address A[23:16] is always equal to the
content of MXAX(0xEA) while another A[15:8] is always equal to P2(0xA0) contents.
2.5.4 Data Pointer Registers
DPTR1 are located in four SFR addresses. Active DPTR register is selected by SEL bit (0x86.0).
If the SEL bit set to ‘0’, DPTR0 (0x83:0x82) is selected, otherwise DPTR1 (0x85:0x84) is
selected.
Data Pointer Extended registers, DPX0, DPX1 and MXAX, hold the most significant part of
When MOVX instruction uses DPTR0/DPTR1 register, the most significant part of the address
Dual data pointer registers are implemented to speed up data block copying. DPTR0 and
MXAM.7
DPX1.7
DPXP.7
7
7
7
7
7
6
6
DPX1.6
MXAX.6
5
5
DPX.6
DPH0(0x83)
DPH1(0x85)
6
6
6
4
4
3
3
DPX1.5
MXAX.5
DPX.5
Figure 2.17 Data Pointer Extended Register
Figure 2.18 Data Pointer Extended Register
Figure 2.21 Data Pointer 1 Register DPTR1
Figure 2.19 MOVX @RI Extended Register
Figure 2.20 Data Pointer Register DPTR0
5
5
5
2
2
1
1
DPX1.4
MXAX.4
DPX.4
4
4
4
0
0
DPTR0(0x83:0x82)
DPTR1(0x85:0x84)
MXAX (0xEA)
DPX0 (0x93)
DPX1 (0x95)
7
7
DPX1.3
MXAX.3
DPX.3
3
3
3
6
6
5
5
DPX1.2
MXAX.2
DPX.2
DPL0(0x82)
DPL1(0x84)
2
2
2
4
4
3
3
DPX1.1
MXAX.1
DPX.1
1
1
2
2
1
1
1
DPX1.0
DPX.0
MXAX.0
Ver. 1.12
0
0
0
0
0
0x0000
0x0000
Reset
Reset
Reset
Reset
0x00
Reset
0x00
0x00
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