W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 84

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
8.3
8.3.1 Mode Register
Bit
MR (Mode Register) [R/W] [0xFE0000] [0x00]
This register is used for S/W reset, ping block mode and PPPoE mode.
7
6
5
4
3
2
1
0
0xFE4728
0xFE4729
0xFE472A
0xFE472B
0xFE472C
0xFE472D
0xFE472E
0xFE472F
0xFE47FF
RST
7
~
Reserved
Reserved
Reserved
Reserved
Reserved
Symbol
PPPoE
Register Description
RST
PB
6
S7_RX_WR0
S7_RX_WR1
S/W Reset
If this bit is ‘1’, internal register will be initialized. It will be automatically
cleared after reset.
Reserved
Reserved
Ping Block Mode
0 : Disable Ping block
1 : Enable Ping block
If the bit is set as ‘1’, there is no response to the ping request.
PPPoE Mode
0 : Disable PPPoE mode
1 : Enable PPPoE mode
If a user uses ADSL without router or etc, the bit should be set as ‘1’ to
connect to ADSL Server. For more detail, refer to the application note,
“How to connect ADSL”.
Reserved
Reserved
Reserved
S7_RX_RD0
S7_RX_RD1
S7_FRAG0
S7_FRAG1
S7_IMR
5
SOCKET 7 Interrupt Mask Register
S7_RX_RD
(SOCKET 7 Receive Memory Read Pointer Register)
S7_RX_WR
(SOCKET 7 Receive Memory Write Pointer Register)
S7_FRAG
(SOCKET 7 Fragment Field Value in IP Header Register)
Reserved
PB
4
PPPoE
Description
3
2
Ver. 1.12
1
0
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