W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 57

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
5.2
5.2.1 Overview
unidirectional. There are no tri-state output pins and internal signals.
Pin
T2/FA1
T2EX/FA2
used to control Timer2 operation, TH2/TL2 (0xCD/0xCC) counter registers, RLDH/RLDL
(0xCB/0xCA) capture registers, and T2CON (0xC8) control register. Timer2 works under three
modes selected by T2CON bits as shown in the table below.
The Timer2 pin functionalities are described in the following table. All pins are
Timer2 of W7100A is fully compatible with the standard 8051 Timer2. A total of five SFR are
RCLK,TCLK
TF2
7
Note: EXF2 – indicates a Falling edge in the T2EX pin when EXEN2=1. Must be cl
X
0
0
1
Timer2
Falling
Active
Falling
EXF2
RCLK - Receive clock enable
TCLK - Transmit clock enable
6
CPRL2
0
1
X
X
Type
eared by software
0: UART receiver is clocked by Timer1 overflow pulses
1: UART receiver is clocked by Timer2 overflow pulses
0: UART transmitter is clocked by Timer1 overflow pulses
I
I
RCLK
Figure 5.13 Timer2 Configuration Register
5
TR2
1
1
1
0
Table 5.4 Timer2 Pin Description
Pu/Pd
TCLK
Table 5.5 Timer2 Modes
Function Description
16-bit auto-reload mode. TF2 bit is set when Timer2
overflows. TH2 and TL2 registers are reloaded with 16-
bit value from RLDH and RLDL.
16-bit capture mode. TF2 bit is set when Timer2
overflows. When EXEN2=1 and T2EX pin is on the falling
edge, TH2 and TL2 register values are stored into RLDH
and RLDL.
Baud rate generator for UART interface
Timer2 is off.
-
-
4
T2CON (0xC8)
EXEN2
Description
Timer2 external clock input
Timer2 capture/reload trigger
3
TR2
2
CT2
1
CPRL2
Ver. 1.12
0
Reset
0x00
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