W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 66

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
7
7.1
The Watchdog Timer is driven by the main system clock that is supplied by a series of dividers
as shown in the Figure below. The divider output is selectable and determines the timeout
intervals. When the timeout is reached, an interrupt flag will be set, and if enabled, a reset
will be occu
flag will activate the interrupts. The reset and interrupt are completely discrete functions
that may be acknowledged separately, together or even ignored depending on the application.
7.2
IE (0xA8) and EIE (0xE8) registers, and high/low priorities can be set in the EIP EIP (0xF8)
register. The IE contains global interrupt system disable (0) / enable (1) bit called EA.
Watchdog interrupt related bits are shown below. An interrupt can be turned on/off by the
EA
7
7
-
Note: EA - Enable global interrupt
Watchdog Timer
Overview
Interrupts
r
red. When interrupt enable bit and global interrupt are enabled, the interrupt
EWDI - Enable Watchdog interrupt
6
-
6
-
Figure 7.3 Extended Interrupt Enable Register
ET2
5
-
5
Figure 7.1 Watchdog Timer Structure
Figure 7.2 Interrupt Enable Register
EWDI
4
ES
4
EIE (0xE8)
EINT5
IE (0xA8)
ET1
3
3
EINT4
EX1
2
2
EINT3
ET0
1
1
EINT2
EX0
Ver. 1.12
0
0
Reset
Reset
0x00
0x00
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