W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 55

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W7100A-64QFN

Manufacturer Part Number
W7100A-64QFN
Description
8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet

Specifications of W7100A-64QFN

Rohs
yes
Interface Type
UART

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5.1.7 Timer1 – Mode0
prescaler). As the all counts (valid bits) roll over from 1 to 0, Timer 1 interrupt flag TF1 is set.
The counted input is enabled to Timer 1 when TCON.6 = 1 and either TMOD.6 = 0 or GATE1 = 1.
(Setting TMOD.7 = 1 allows Timer 1 controlled by external input GATE1, to facilitate pulse
width measurements). The 13-bit register consists of 8 bits TH1 and the lower 5 bits of TL1.
The upper 3 bits of TL1 are indeterminate and should be ignored. Refer to the following
Figure for detail.
5.1.8 Timer1 – Mode1
Mode1 is shown in the Figure below.
In this mode, the Timer1 register is configured as a 13-bit register (8bit: Timer, 5bit:
Mode1 is the same as Mode0, except that the timer register is running with all 16 bits.
Figure 5.11 Timer/Counter1, Mode1: 16-Bit Timers/Counters
Figure 5.10 Timer/Counter1, Mode0: 13-Bit Timer/Counter
Ver. 1.12
55

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