W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 44

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
bit in IE(0xA8) and EIE(0xE8) registers. The IE register contains global interrupt system
disable(0)/enable(1) bit called EA.
result by hardware. That is, interrupts can be generated or cancelled by software. The only
exceptions are the request flags IE0 and IE1. If the external interrupt 0 or 1 are programmed
as level-activated, the IE0 and IE1 are controlled by the external source pins nINT0/FA6 and
nINT1/FA7 respectively.
All these bits which generate interrupts can be set or cleared by software, with the same
TF1
EA
7
7
-
7
Note: EA - Enable global interrupt
Note: PX0 - INT0 priority level control (high level at 1)
Note: IT0 - INT0 level (at 0)/edge (at 1) sensitivity
EX0 - Enable INT0 interrupt
ET0 - Enable Timer0 interrupt
EX1 - Enable INT1 interrupt
ET1 - Enable Timer1 interrupt
ES – Enable UART interrupt
ET2 - Enable Timer2 interrupt
PT0 - Timer0 priority level control (high level at 1)
PX1 - INT1 priority level control (high level at 1)
PT1 - Timer1 priority level control (high level at 1)
PS - UART priority level control (high level at 1)
PT2 – Timer2 priority level control (high level at 1)
Unimplemented bit - Read as 0 or 1
TR1
IT1 - INT1 level (at 0)/edge (at 1) sensitivity
IE0 - INT0 interrupt flag is automatically cleared when processor branches to
6
6
-
-
6
Figure 3.3 Timer0, 1 Configuration Register
PT2
ET2
TF0
5
5
5
Figure 3.2 Interrupt Priority Register
Figure 3.1 Interrupt Enable Register
TR0
PS
ES
4
4
4
TCON (0x88)
IE (0xA8)
IP (0xB8)
ET1
PT1
IE1
3
3
3
PX1
EX1
IT1
2
2
2
PT0
ET0
IE0
1
1
1
EX0
PX0
Ver. 1.12
IT0
0
0
0
Reset
Reset
Reset
0x00
0x00
0x00
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