W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 68

• Manufacturer Part Number: W7100A-64QFN
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A-64QFN

• Rohs: yes
• Interface Type: UART

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
7.4
and interrupt functions disabled (EWDI = 0), the timer counts up to pre-programmed interval
in WD[1:0] which will enable the Watchdog interrupt flag. By resetting the RWT bit, this timer
can operate in polled timeout mode. The WDIF bit can be cleared by software or reset. The
Watchdog interrupt is available for application which requires a long timer. The interrupt is
enabled by using the EWDI (Enable WatchDog timer Interrupt = EIE.4) bit. When a timeout
occurs, the Watchdog Timer will set the WDIF bit (WDCON.3), and an interrupt will occur if
the global interrupt enable (EA) is set. Note that WDIF is set to 512 clocks before a
potential Watchdog reset. The Watchdog interrupt flag indicates the source of the interrupt,
and must be cleared by software. When the Watchdog interrupt is used properly, the
Watchdog reset allows the interrupt software to monitor the system for any errors.
7.5
can use the Watchdog timer as a system monitor using this function. For example, assuming
that an unexpected code was running, there is no RWT clear routine because this code is not
designed by user; resulting a Watchdog timeout to occur, and the W7100A will reset. User can
escape unexpected state by using this method.
7.6
be utilized as a reset source, interrupt source, software polled timer or any combination of
the three. Both the reset and interrupt have status flags. The Watchdog also has a bit which
restarts the timer. The table below shows the bit locations with descriptions.
timer. Control bits that support Watchdog operation are described in next subsections.
The Watchdog Timer is a free running timer. In timer mode with reset disabled (EWT = 0)
If the EWT bit of WDCON was set, W7100A will reset when a Watchdog timeout occurs. User
The Watchdog Timer has several SFR bits that are used during its operation. These bits can
The Watchdog Timer is not disabled during a Watchdog timeout reset, but it restarts the
Bit Name
WD[1:0]
WTRF
EWDI
PWDI
WDIF
RWT
EWT
Simple Timer
System Monitor
Watchdog Related Registers
Register
WDCON
CKCON
EIE
EIP
Table 7.2 Summary for Watchdog Related Bits
Bit Position
CKCON.7-6
WDCON.0
WDCON.1
WDCON.2
WDCON.3
EIE.4
EIP.4
Description
Enable Watchdog Timer Interrupt
Priority of Watchdog Timer Interrupt
Watchdog Interval
Reset Watchdog Timer
Enable Watchdog Timer reset
Watchdog Timer reset flag
Watchdog Interrupt flag
Ver. 1.12
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