DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 100

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 5: Implementing CPLD Designs
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2.
While these pin locations are specific to the board in the CPLD Design Kit, this alone is not
enough to get the design working on the board. For a challenge and to get this design
working on the board in the CPLD Design Kit, please refer to the end of this chapter.
software will create a constraints file and call it “top.ucf.” It will be associated with
your top level source file.
Notice that the Translate step in the Implement Design section runs
automatically. This is because the implementation stage must see the netlist before it
can offer you the chance to constrain sections of the design. When translate has
completed, the Xilinx PACE (Pinout Area and Constraints Editor) tool opens. If there
are already constraints in the UCF file, these will be imported by PACE and displayed.
As we have an empty UCF file, nothing exists for PACE to import. In the Design Object
List, you can enter a variety of constraints on the I/O pins used in the design. PACE
recognizes the five pins in the design and displays them in the list.
Click in the Loc area next to each signal and enter the following location constraints:
clock
reset
red_light
green_light
amber_light
Figure 5-5: Enter Location Constraints
www.xilinx.com
Figure 5-4: Assign Package Pins
p38
p143
p11
p13
p12
Programmable Logic Design
June 12, 2006
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