DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 38

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 2: Xilinx Silicon Solutions
28
Table 2-6: Spartan-3E FPGA Family Overview
Digital clock management (DCM)
Global routing resources
Programmable output drive
System Gates
Logic Cells
Dedicated Multipliers
Block RAM Blocks
Block RAM Bits
Distributed RAM Bits
DCMs
Max Differential I/O
Max Single Ended I/O
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
Device
XC3S100E
www.xilinx.com
2,160
100K
72K
15K
108
108
40
66
4
4
2
XC3S250E
Eliminate on-chip and board level clock delay,
simultaneous multiply and divide, reduction of
board level clock speed and number of board level
clocks, adjustable clock phase for ensuring
coherency
Distribution of clocks and other signals with very
high fanout throughout the device
Improves signal integrity, achieving right trade off
between Tco and ground bounce
5,508
250K
216K
38K
172
108
158
172
12
12
68
66
92
4
XC3S500E
10,476
500K
360K
73K
232
158
190
232
20
20
92
92
4
Programmable Logic Design
XC3S1200E XC3S1600E
1200K
19,512
504K
136K
124
304
190
250
304
28
28
8
33,192
1600K
June 12, 2006
648K
231K
156
376
250
304
376
36
36
8
R