DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 106

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 5: Implementing CPLD Designs
Implementation
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However, we will not use these features in this tutorial. For more information on the use of
CoolRunner-II CPLDs, and their advanced features, visit www.xilinx.com/apps/cpld.htm for
a number of application notes, often including free code examples.
To implement the design, you must re-run Translate so the new constraints can be read.
1.
2.
3.
4.
5.
Click on the “+” next to Implement Design in the Process window.
The implementation steps are now visible. An orange question mark indicates that
translate is now out of date and should be re-run.
A right-click on Implement Design allows you to edit the Properties for each
particular step. Notice that the Fitting category is selected in
The Help button will explain the operation of each field. You can set the default I/O
standard under the Fitting category of the Process Properties window, as
shown in
In this case, we will set the I/O Voltage Standard to LVCMOS18 so that all of our
pins are configured to be compliant with the LVCMOS 1.8V standard. If this is all you
want to change, click OK. If you would like to examine the options of the other
Categories, click through them.
You can implement your design by double-clicking on Implement Design. When
there is a green check mark next to Implement Design, the design has completed the
implementation stage.
The timing analysis is performed by default on the design. To look at the Timing
Report, expand the Optional Implementation Tools branch in the Process
Figure
Figure 5-13: Process Properties – Implement Design
5-13.
www.xilinx.com
Programmable Logic Design
Figure 5-13
June 12, 2006
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