DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 70
DO-CPLD-DK-G
Manufacturer Part Number
DO-CPLD-DK-G
Description
KIT DESIGN CPLD W/BATT HOLDER
Manufacturer
Xilinx Inc
Series
CoolRunner™- IIr
Type
CPLDr
Specifications of DO-CPLD-DK-G
Contents
Proto Board, Download Cable, Samples, Software
For Use With/related Products
CoolRunner-ll, XC9500XL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1512
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Chapter 4: WebPACK ISE Design Entry
60
7.
8.
540ns clock period or a Clock High and Clock Low time of 270ns, Input Setup and
Output Valid times of 50ns and an Initial Testbench Length of 10000ns.
Click Finish
Note that the blue cells are for entering input stimulus and the yellow cells are for
entering expected response.
When entering a stimulus, clicking the left mouse button on the cell will cycle through
the available values for that cell. Click on the first blue box in the reset line. This will
Figure 4-9: Initial Timing and Clock Wizard
www.xilinx.com
Figure 4-10: HDL Bencher Window
Programmable Logic Design
June 12, 2006
R
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