DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 68

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 4: WebPACK ISE Design Entry
58
Save the Counter Module
The counter module should now look like
several new features are available in the Source Editor window.
bar on the left side of the Source Editor window will bring up a menu of these features.
can toggle the line numbers in the side bar on or off and place bookmarks to mark lines of
interest in the source file.
A typical VHDL module consists of library declarations, an entity, and an architecture. The
library declarations are needed to tell the compiler which packages are required. The entity
declares all ports associated with the design. Count (3 down to 0) means that count is a 4-
bit logic vector.
This design has two inputs – clock and reset – and one output, a 4-bit bus called “count.”
The actual functional description of the design appears after the begin statement in the
architecture. The function of this design is to increment a signal “count” when clock = 1
and there is an event on the clock. This is resolved into a positive edge. The reset is
asynchronous as is evaluated before the clock action.
The area still within the architecture – but before the begin statement – is where
declarations reside. We’ll give some examples of component and signal declarations later
in this chapter.
You can now simulate the counter module of the design. With “counter.vhd” highlighted
in the Source window, the Process window will give all the available operations for that
particular module. A VHDL file can be synthesized and then implemented through to a
b. Addition of the line count <= "0000";
c.
d. Changing if to elsif before clock='1'
Addition of reset in the process sensitivity list
Figure 4-7: Counter in VHDL Window
www.xilinx.com
Figure
4-7. For the purposes of debugging code,
Programmable Logic Design
A right-click in the gray
June 12, 2006
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