DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 67

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
R
Edit the Counter Module
In this tutorial, the template uses the signal name “clk.” The design requires the signal to
be called “clock.” The counter in the template is too complex for this particular
requirement, so some sections are deleted. To use the language template:
1.
2.
3.
4.
5.
Notice the color-coding used in the HDL Editor. The green text indicates a comment. The
commented text in this template shows which libraries are required in the VHDL header.
The port definitions are required if this counter was used in its entirety. As you have
already created the entity, this information is not required. You can delete the green
comments if you wish.
The counter from the template shows a loadable bidirectional counter. For this design, only
a 4-bit up counter is required.
1.
2.
Note the changes are:
In the HDL Editor place the cursor between begin and end Behavioral.
Open the language templates by clicking the button
You can also access the language template from the Edit → Language Template
menu.
Navigate to the Simple Counter in the Language Templates as follows:
VHDL → Synthesis Constructs → Coding Examples → Counters →
Binary → Up Counters → Simple Counter
With Simple Counter highlighted select:
Edit
Select the Counter tab on the HDL Editor. This will switch you back to the HDL
Editor while leaving the Language Template open in another tab.
You will see the simple counter code has been entered into file.
Remove the brackets <> around the words “clock” and “count” in the code you have
just pasted into the Counter.vhd file.
The next step is to edit the code to include a reset. Currently, the code looks like this:
process (clock)
begin
end process;
To add in a reset line is simple. You will need to edit the code to look like this:
process (clock, reset)
begin
end process;
a.
if clock='1' and clock'event then
end if;
elsif clock='1' and clock'event then
end if;
Addition of if reset='1' then
if reset='1' then
→
count <= count + 1;
count <= "0000";
Use in File
count <= count + 1;
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Design Entry
57