DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 101

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
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When a pin is highlighted in the Design Object List, the pin to which it is
“Locked” is highlighted in the Package Pins view. If you roll the cursor over the pin, it
will display information about it.
Save the PACE session and exit the PACE tool. It is now possible to see the constraints
in the UCF file.
Now, under the User Constraints tab, double-click Edit Constraints (Text)
in the Process window. The UCF file will open in the main window of the ISE Project
Navigator. The constraints entered into PACE can be seen in
To force a signal onto a global resource, you can apply the BUFG constraint. In this
case, we will apply the BUFG constraint to the clock signal. Enter the following syntax
in the text file:
NET "clock" BUFG=CLK;
Save and the text file.
The next step is to create timing constraints. With the UCF highlighted in the Source
window, double-click on Create Timing Constraints in the Process window.
If you do not see the UCF file in the Sources window, add it by using Project
Figure 5-7: Text Constraints Imported from PACE
Figure 5-6: Section of Pace Display
www.xilinx.com
Figure
Constraints Editor
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