DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 37

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
Spartan-3 Features and Benefits
R
Table 2-4: Spartan-3 FPGA Family Overview
Table 2-5: Spartan-3 Features and Benefits
System Gates
Logic Cells
Dedicated Multipliers
Block RAM Blocks
Block RAM Bits
Distributed RAM Bits
DCMs
I/O Standards
Max Single Ended I/O
• Immunity to Temperature and
• Eliminates Stub Reflection
• Increases System Reliability
FPGA fabric and routing, up to
5,000,000 system gates
Block RAM – 18k blocks
Distributed RAM
Shift register mode (SRL16)
Dedicated 18 x 18 multiplier blocks
Single-ended signalling (up to 622
Mbps) – LVTTL, LVCMOS, GTL,
GTL+, PCI, HSTL-I, II, III, SSTL-I,II
Differential signalling (up to 622
Mbps) - LVDS, BLVDS, Ultra LVD,
SRSDS and LDT
Voltage Changes
Device
Spartan-3 Feature
XC3S50
1,728
50K
72K
12K
124
24
4
4
2
www.xilinx.com
XC3S200
4,320
200K
216K
30K
173
12
12
24
4
XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000
Temperature and voltage variations lead to
significant impedance mismatches. XCITE
technology dynamically adjusts on-chip
impedance to such variations reducing and
improving reliability
Improves discrete termination techniques by
eliminating the distance between the package pin
and resistor.
Fewer components on board, deliver higher
reliability
Allows for implementation of system level function
blocks, high on-chip connectivity and high-
throughput
Enables implementation of large packet
buffers/FIFOs, line buffers
For implementing smaller FIFOs/Buffers, DSP
coefficients
16-bit shift register ideal for capturing high speed or
burst mode data and to store data in DSP and
encryption applications e.g. fast pipelining
High speed DSP processing; use of multipliers in
conjunction with fabric allows for ultra-fast, parallel
DSP operations
Connectivity to commonly used chip-to-chip,
memory (SRAM, SDRAM) and chip-to- backplane
signalling standards; eliminates the need for
multiple translation ICs
Differential signalling at low cost – bandwidth
management (saving the number of pins, reduced
power consumption, reduced EMI, high noise
immunity
8,064
400K
288K
56K
264
16
16
24
4
17,280
1000K
432K
120K
391
24
24
24
4
29,952
1500K
576K
208K
487
32
32
24
4
Benefit
46,080
2000K
720K
320K
565
40
40
24
4
Platform FPGAs
62,208
1,728K
4000K
432K
712
96
96
24
4
74,480
1,872K
5000K
520K
104
104
784
24
4
27