DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 26

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 2: Xilinx Silicon Solutions
16
Advanced Interconnect Matrix (AIM)
either double data rate capability or the ability to distribute a slower clock (thereby saving
power). For single-edge clocking or latching, either clock polarity may be selected per
macrocell.
CoolRunner-II macrocell details are shown in
in the in figure, except the trapezoidal multiplexers have input selection from statically
programmed configuration select lines (not shown). Xilinx application note XAPP376
gives a detailed explanation of how logic is created in the CoolRunner-II CPLD family.
When configured as a D-type flip-flop, each macrocell has an optional clock enable signal
permitting state hold while a clock runs freely. Note that control terms are available to be
shared for key functions within the function block, and are generally used whenever the
exact same logic function would be repeatedly created at multiple macrocells. The control
term product terms are available for function block clocking (CTC), function block
asynchronous set (CTS), function block asynchronous reset (CTR), and function block
output enable (CTE).
You can configure any macrocell flip-flop as an input register or latch, which takes in the
signal from the macrocell’s I/O pin and directly drives the AIM. The macrocell
combinatorial functionality is retained for use as a buried logic node if needed.
AIM is a highly connected low-power rapid switch directed by the software to deliver a set
of as many as 40 signals to each function block for the creation of logic. Results from all
function block macrocells, as well as all pin inputs, circulate back through the AIM for
additional connection available to all other function blocks, as dictated by the design
software. The AIM minimizes both propagation delay and power as it makes attachments
to the various function blocks.
FB Inputs
FB Inputs
from AIM
from AIM
40
40
Figure 2-7: CoolRunner-II Macrocell Architecture
PLA Array
PLA Array
PTC
PTC
49
49
P terms
P terms
4
4
Control
Control
Terms
Terms
PTB
PTB
PTA
PTA
www.xilinx.com
GND
GND
VCC
VCC
CTC
CTC
PTC
PTC
GCK0
GCK0
GCK1
GCK1
GCK2
GCK2
from I/O Block
from I/O Block
(Fast Input)
(Fast Input)
Figure
CTS
CTS
CTS
GSR
GSR
GSR
GND
GND
GND
PTA
PTA
PTA
PTA
PTA
PTA
CTR
CTR
CTR
GSR
GSR
GSR
GND
GND
GND
Macrocell
Macrocell
PTC
PTC
2-7. Standard logic symbols are used
CE
CE
CK
CK
D/T
D/T
R
R
S
S
FIF
FIF
DualEDGE
DualEDGE
Latch
Latch
Programmable Logic Design
Feedback to AIM
Feedback to AIM
Q
Q
to I/O
to I/O
to I/O
June 12, 2006
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