DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 25

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
CoolRunner-II Macrocell
R
The PLA is different – and better. First, any p-term can be attached to any OR gate inside
the function block macrocell(s). Second, any logic function can have as many p-terms as
needed attached to it within the function block, to an upper limit of 56. Third, you can
reuse product terms at multiple macrocell OR functions so that within a function block,
you need only create a particular logical product once, but you can reuse it as many as 16
times within the function block. Naturally, this works well with the fitting software, which
identifies product terms that can be shared.
The software places as many functions as it can into function blocks. There is no need to
force macrocell functions to be adjacent or have any other restriction except for residing in
the same function block, which is handled by the software. Functions need not share a
common clock, common set/reset, or common output enable to take full advantage of the
PLA. In addition, every p-term arrives with the same time delay incurred. There are no
cascade time adders for putting more product terms in the function block. When the
function block p-term budget is reached, a small interconnect timing penalty routes signals
to another function block to continue creating logic. Xilinx design software handles all this
automatically.
The CoolRunner-II CPLD macrocell is extremely efficient and streamlined for logic
creation. You can develop SOP logic expressions comprising as many as 40 inputs and span
56 product terms within a single function block. The macrocell can further combine the
SOP expression into an XOR gate with another single p-term expression. The resulting
logic expression’s polarity is also selectable. The logic function can be pure combinatorial
or registered, with the storage element operating selectively as a D or T flip-flop, or
transparent latch. Available at each macrocell are independent selections of global,
function- block level, or local p-term-derived clocks, sets, resets, and output enables. Each
macrocell flip-flop is configurable for either single edge or DualEDGE clocking, providing
Can NOT share
Can NOT share
Can NOT share
common logic
common logic
common logic
Indicates ‘used’ junction
Indicates ‘used’ junction
Indicates ‘used’ junction
PAL: Requires 4 pt’s!
PAL: Requires 4 pt’s!
Indicates ‘unused’ junction
Indicates ‘unused’ junction
Indicates ‘unused’ junction
Indicates ‘fixed’ junction
Indicates ‘fixed’ junction
Indicates ‘fixed’ junction
A
A
A
B
B
B
Figure 2-6: Logic Allocation – Typical PAL vs. PLA
C
C
C
www.xilinx.com
X
X
X
Y
Y
Y
A
A
A
X = A & B # C
X = A & B # C
Y = A & B # !C
Y = A & B # !C
PLA: Requires only 3 pt’s!
PLA: Requires only 3 pt’s!
PLA
PLA
Common logic may be shared
Common logic may be shared
CoolRunner-II Low-Power CPLDs
B
B
B
in CoolRunner-II
in CoolRunner-II
C
C
C
X
X
X
Y
Y
Y
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