DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 82

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 4: WebPACK ISE Design Entry
72
8.
9.
10. Next is the instantiation of the state machine module. Enter the following text under
11. Declare a signal called “timer” by adding the following line above the component
Rearrange the component declaration so that it lies before the begin statement in the
architecture. Rearrange the instantiation so that it lies between the begin and end
statement (see
Now we need to manually enter the component declaration and instantiation for the
state machine as follows. Beneath the Counter component declaration enter the
following:
the Counter instantiation.
declarations inside the architecture:
signal timer : std_logic_vector(3 downto 0);
COMPONENT stat_mac
PORT(
END COMPONENT;
Inst_stat_mac: stat_mac PORT MAP(
);
timer : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
reset : IN std_logic;
amb : OUT std_logic;
rd : OUT std_logic;
grn : OUT std_logic
);
timer => ,
clk => ,
reset => ,
amb => ,
grn => ,
rd =>
Figure 4-34: Instantiation Template Code Added to Top File
Figure 4-34
www.xilinx.com
for reference).
Programmable Logic Design
June 12, 2006
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