DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 29

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
Design Security
R
DualEDGE
CoolCLOCK
clock nets. The signal is buffered and driven to multiple traces with minimal loading and
skew.
Each macrocell has the ability to double its input clock switching frequency.
shows the macrocell flip-flop with the DualEDGE option (doubled clock) at each
macrocell. The source to double can be a control term clock, a product term clock, or one of
the available global clocks. The ability to switch on both clock edges is vital for a number
of synchronous memory interface applications as well as certain double data rate I/O
applications.
In addition to the DualEDGE flip-flop, you can gain additional power savings by
combining the clock division circuitry with the DualEDGE circuitry. This capability is
called CoolCLOCK and is designed to reduce clocking power within the CPLD. Because
the clock net can be a significant power drain, you can reduce the clock power by driving
the net at half frequency, and then doubling the clock rate using DualEDGE triggering at
the macrocells.
cascading, with the divider and DualEDGE flip-flop working together.
You can secure your designs during programming to prevent either accidental overwriting
or pattern theft via readback. CoolRunner-II CPLDs have four independent levels of
security provided on-chip, eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing the entire device. Additional
details are omitted intentionally.
CDRST
(GCK2)
CDRST
Global
GCK2
Clock
Figure 2-11
Divide
by 2
Divide
Clock
Input
Figure 2-10: CoolRunner-II Clock Division
www.xilinx.com
DIV2
illustrates how CoolCLOCK is created by internal clock
2,4,6,…,16
Figure 2-11: CoolCLOCK
Divide
Clock
By
Routing
Divided
Device
Global
Clock
DIV16
DIV2
DIV4
CoolRunner-II Low-Power CPLDs
Macrocell
D/T/L
T
Latch
D
DualEDGE
x378_01_041202
x378_03_041202
to FB 1
to FB n
Figure 2-7
Q
19