DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 138

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

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HDL – Hardware Description Language.
Hierarchical Design – Design description in multiple layers, from the highest (overview) to
the lowest (circuit details). Alternative: flat design, where everything is described at the
same level of detail. Incremental design making small design changes while maintaining
most of the layout and routing.
Interconnect – Metal lines and programmable switches that connect signals between logic
blocks and between logic blocks and the I/O.
IOB or I/O – Input/Output block. Logic block with features specialized for interfacing with
the PC board.
ISO9000 – An internationally recognized quality standard. Xilinx is certified to ISO9001 and
ISO9002.
IP – Intellectual Property. In the legal sense: patents, copyrights, and trade secrets. In
integrated circuits: pre-defined large functions, called cores, that help you complete large
designs faster.
ISP – In-System Programmable device. A programmable logic device that can be
programmed after it has been connected to (soldered into) the system PC board. Although
all SRAM-based FPGAs are naturally ISP, this term is only used with certain CPLDs, to
distinguish them from the older CPLDs that must be programmed in programming
equipment.
JTAG – Joint Test Action Group. Older name for IEEE 1149.1 Boundary Scan, a method to
test PC boards and ICs.
LogiBLOX – Formerly called X-Blox. Library of logic modules, often with user-definable
parameters, like data width. Very similar to LPM.
Logic Cell – Metric for FPGA density. One logic cell is one 4-input look-up table plus one
flip-flop.
LPM – Library of Parameterized Modules. Library of logic modules, often with user-
definable parameters, like data width. Very similar to LogiBlox.
LUT – Look-Up Table. Also called function generator with N inputs and one output. Can
implement any logic function of its N inputs. N is between 2 and 6; 4-input LUTs are most
popular.
Macrocell – The logic cell in a sum-of-products CPLD or PAL/GAL.
Mapping – Process of assigning portions of the logic design to the physical chip resources
(CLBs). With FPGAs, mapping is a more demanding and more important process than with
gate arrays.
MTBF – Mean Time Between Failure. The statistically relevant up-time between equipment
failure. See also FIT.
Netlist – Textual description of logic and interconnects. See also XNF and EDIF.
NRE – Non-Recurring Engineering charges. Startup cost for the creation of an ASIC, gate
array, or HardWire. Pays for layout, masks, and test development. FPGAs and CPLDs do
not require NRE.
Optimization – Design change to improve performance. See also Synthesis.
OTP – One-Time Programmable. Irreversible method of programming logic or memory.
Fuses and anti-fuses are inherently OTP. EPROMs and EPROM-based CPLDs are OTP if
their plastic package blocks the ultraviolet light needed to erase the stored data or
configuration.
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Programmable Logic Design
June 12, 2006