DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 57

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Advanced Design Techniques
Programmable Logic Design
June 12, 2006
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Debug Verification
Debug verification tools speed up the process of viewing, identifying, and correcting
design problems at different stages of the design cycle. Debug verification includes the
ability to view, “live,” all internal signals and nodes within an FPGA. These tools can also
assist in HDL-based designs by checking coding style for optimum performance. The
following debug verification tools are supported:
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Board-Level Verification
Using board-level verification tools ensures that your design performs as intended once
integrated with the rest of the system. The Xilinx ISE environment supports the following
board-level verification tools:
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As your FPGA requirements grow, your design problems can change. High-density design
environments mean multiple teams working through distributed nodes on the same
project, across the aisle or in different parts of the world. ISE software’s advanced design
options are targeted at making high-density designs as easy to realize as the smallest glue
logic.
Floorplanner – The Xilinx high-level floorplanner is a graphic planning tool that lets you
map your design onto the target chip. Floorplanning can efficiently drive your high-
density design process.
Modular Design – This gives you the ability to partition a large design into individual
modules. Each module can then be floorplanned, designed, implemented, and locked until
the remaining modules are finished.
Partial Reconfigurability – Useful for applications requiring the loading of different
designs into the same area of the device, partial reconfiguration allows you to flexibly
change portions of a design without having to reset or completely reconfigure the entire
device.
Internet Team Design – This allows managers to drive each team and its design module
from a standard Internet browser using the corporate intranet structure.
HDL Bencher™
ISE Simulator
ModelSim XE
StateBench
HDL Simulation Libraries
FPGA Editor Probe
ChipScope ILA
ChipScope Pro
IBIS Models
Tau
BLAST
Stamp Models
iMPACT
www.xilinx.com
Advanced Design Techniques
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