DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 110

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 5: Implementing CPLD Designs
Configuration
100
4.
5.
The CPLD Design Kit comes with its own JTAG cable which is required to configure the
device from the iMPACT programmer.
1.
With “top_tb.vhd” (or “top_sch_tb.vhd” for schematic flow) selected in the Sources
window, expand the Xilinx ISE Simulator tree in the Process window and double-
click on Simulate Post Fit Model.
ISE Simulator will open, but this time implementing a different script file and
compiling a post-route VHDL file (time_sim.vhd). “Time_sim.vhd” is a very low-level
VHDL file generated by the implementation tools. It references the resources within
the CPLD and takes timing information from a separate file.
Use the zoom features and cursors to measure the added timing delays.
Make sure the cable is plugged into the computer and the board. Also ensure that the
board is powered up with the batteries or a suitable power supply.
Figure 5-17: Post-Fit Simulation Waveform
www.xilinx.com
Programmable Logic Design
June 12, 2006
R