DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 28

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 2: Xilinx Silicon Solutions
18
Additional Clock Options: Division, DualEDGE, and CoolCLOCK
Division
consumption. Disabling these switches enables you to complete your design and choose
which sections will participate in the DataGATE function.
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The DataGATE logic function drives an assertion rail threaded through medium- and
high-density CoolRunner-II CPLD parts. You can select which inputs to block under the
control of the DataGATE function, effectively blocking controlled switching signals so that
they do not drive internal chip capacitances. Output signals that do not switch are held by
the bus hold feature. You can choose any set of input pins can be chosen to participate in
the DataGATE function.
Figure 2-9
assertion rail. It can have any desired logic function on it – something as simple as
mapping an input pin to the DataGATE function or as complex as a counter or state
machine output driving the DataGATE I/O pin through a macrocell. When the DataGATE
rail is asserted low, any pass transistor switch attached to it is blocked. Each pin has the
ability to attach to the AIM through a DataGATE pass transistor, and be blocked. A latch
automatically captures the state of the pin when it becomes blocked. The DataGATE
assertion rail threads throughout all possible I/Os, so each can participate if chosen. One
macrocell is singled out to drive the rail, and that macrocell is exposed to the outside world
(through a pin) for inspection. If the DataGATE function is not needed, this pin is an
ordinary I/O.
Circuitry has been included in the CoolRunner-II CPLD architecture to divide one
externally supplied global clock by standard values, with options for division by 2, 4, 6, 8,
10, 12, 14, and 16 (see
resulting clock produced will be 50% duty cycle for all possible divisions. Note that a
synchronous reset is included to guarantee that no runt clocks can get through to the global
Input
Available on all input pins (except JTAG pins)
Available for all I/O types
Selectable on a per pin basis
Data latch holds last valid pin value
DataGATE allows additional power savings
♦
DataGATE can also be used for debugging and hot plug input
Pin
ability to disable active board inputs
shows how DataGATE function works. One I/O pin drives the DataGATE
Figure 2-9: DataGATE Function in CoolRunner-II CPLDs
Assertion Rail
DataGATE
Figure
www.xilinx.com
2-10). This capability is supplied on the GCK2 pin. The
Configuration
Bit
Data Latch
Programmable Logic Design
June 12, 2006
to AIM
R