DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 91
DO-CPLD-DK-G
Manufacturer Part Number
DO-CPLD-DK-G
Description
KIT DESIGN CPLD W/BATT HOLDER
Manufacturer
Xilinx Inc
Series
CoolRunner™- IIr
Type
CPLDr
Specifications of DO-CPLD-DK-G
Contents
Proto Board, Download Cable, Samples, Software
For Use With/related Products
CoolRunner-ll, XC9500XL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1512
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Programmable Logic Design
June 12, 2006
I/O Markers
R
12. Select the Add Net Names tool from the Drawing toolbar.
13. Type “clock” in the Name bar of the Options tab (Processes window) and then click on
14. To add net names to wires that will be connected to your FPGA/CPLD I/Os, place the
15. Select the Add I/O Marker tool from the Drawing toolbar.
16. With the Input type selected, click and drag around all the inputs to which you want to
the net in the schematic editor.
net name on the end of the hanging wire. Finish adding the net names “reset”,
“amber_light”, “green_light” and “red_light”. ECS recognizes that count(3:0) and
TIMER(3:0) are buses, and so connects them together with a bus rather than a single
net.
add input markers. Repeat for the outputs but select Output type.
www.xilinx.com
Figure 4-48: Add Net Name
Top-Level Schematic Designs
81
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