DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 69

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Functional Simulation
Programmable Logic Design
June 12, 2006
R
bitstream. Normally, a design consists of several lower-level modules wired together by a
top-level file. This design currently only has one module that can be simulated.
To simulate a VHDL file, you must first create a testbench.
1.
2.
3.
4.
5.
6.
From the Project menu, select “New Source” as before.
Select “Test Bench Waveform” as the source type and give it the name “counter_tb.”
Click the Next> button.
The testbench is going to simulate the counter module, so when asked which source
you want to associate the source with, select “Counter” and click the Next> button.
Review the information and click the Finish button.
The HDL Bencher tool now reads in the design. The “Initialize Timing” box sets the
frequency of the system clock, setup requirements, and output delays. The demoboard
in the CPLD Design Kit has a 1.842MHz oscillator on the board. So, we shall enter a
www.xilinx.com
Figure 4-8: New Source Window
Functional Simulation
59