DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 30

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 2: Xilinx Silicon Solutions
XC9500XL CPLD Overview
20
Flexible Pin-Locking Architecture
Full IEEE 1149.1 JTAG Development and Debugging Support
•
The high-performance, low-cost XC9500XL family of Xilinx CPLDs are targeted for
leading-edge systems that require rapid design development, longer system life, and
robust field upgrade capability. The 3.3V XC9500XL family ranges in density from 36 to 288
macrocells.
These devices are In-System Programmable (ISP), which allows manufacturers to perform
unlimited design iterations during the prototyping phase, extensive system in-board
debugging, program and test during manufacturing, and field upgrades.
Based on advanced process technologies, the XC9500XL CPLD provides fast, guaranteed
timing; superior pin locking; and a full JTAG-compliant interface. All XC9500XL devices
have excellent quality and reliability characteristics with a 10,000 program/erase cycle
endurance rating and 20-year data retention.
XC9500XL devices, in conjunction with our fitter software, give you the maximum in
routeability and flexibility while maintaining high performance. The architecture is
feature-rich, including individual product term (p-term) output enables, three global
clocks, and more p-terms per output than any other CPLD. The proven ability of the
architecture to adapt to design changes while maintaining pin assignments has been
demonstrated in countless real-world customer designs.
The JTAG capability of the XC9500XL CPLD is the most comprehensive of any CPLD on
the market. It features the standard support including BYPASS, SAMPLE/PRELOAD, and
EXTEST. Additional Boundary Scan instructions, not found in any other CPLD, include
INTEST (for device functional test), HIGHZ (for bypass), and USERCODE (for program
tracking), for maximum debugging capability.
The XC9500XL family is supported by a wide variety of industry-standard third-party
development and debugging tools including Corelis, JTAG Technologies, and Asset
Intertech. These tools allow you to develop Boundary Scan test vectors to interactively
analyze, test, and debug system failures. The family is also supported on all major ATE
platforms, including Teradyne, Hewlett Packard, and Genrad.
Table 2-2: XC9500XL Product Overview
Macrocells
Usable Gates
Registers
T
PD
Four independent levels of security
♦
♦
♦
♦
(ns)
Hidden and scattered
Affect different modes
Interconnects are buried
Multiple programming bits
www.xilinx.com
XC9536XL
800
36
36
5
XC9572XL
1,600
72
72
5
XC95144XL
Programmable Logic Design
3,200
144
144
5
XC95288XL
June 12, 2006
6,400
288
288
6
R