DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 140

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

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Static Timing – Detailed description of on-chip logic and interconnect delays.
Sub-Micron – The smallest feature size is usually expressed in micron (μ = millionth of a
meter, or thousandth of a millimeter) The state of the art is moving from 0.35μ to 0.25μ, and
may soon reach 0.18μ. The wavelength of visible light is 0.4 to 0.8μ. 1 mil = 25.4μ.
Synchronous – Circuitry that changes state only in response to a common clock, as
opposed to asynchronous circuitry that responds to a multitude of derived signals.
Synchronous circuits are easier to design, debug, and modify, and tolerate parameter
changes and speed upgrades better than asynchronous circuits.
Synthesis – Optimization process of adapting a logic design to the logic resources
available on the chip, like LUTs, longline, and dedicated carry. Synthesis precedes
mapping.
SystemI/O – Technology incorporated in Virtex-II FPGAs that uses the SelectIO-Ultra
blocks to provide the fastest and most flexible electrical interfaces available. Each I/O pin
is individually programmable for any of the 19 single-ended I/O standards or six differential
I/O standards, including LVDS, SSTL, HSTL II, and GTL+. SelectIO-Ultra technology
delivers 840 Mbps LVDS performance using dedicated DDR registers.
TBUFs – Buffers with a tri-state option, where the output can be made inactive. Used for
multiplexing different data sources onto a common bus. The pull- down-only option can use
the bus as a wired AND function.
Timing – Relating to delays, performance, or speed.
Timing Driven – A design or layout method that takes performance requirements into
consideration.
UART – Universal Asynchronous Receiver/Transmitter. An 8-bit-parallel- to-serial and
serial-to-8-bit-parallel converter, combined with parity and start- detect circuitry and
sometimes even FIFO buffers. Used widely in asynchronous serial communications
interfaces such as modems.
USB – Universal Serial Bus. A new, low-cost, low-speed, self-clocking bit- serial bus (1.5
MHz and 12 MHz) using four wires (Vcc, ground, differential data) to daisy-chain as many
as 128 devices.
VME – Older bus standard, popular with MC68000-based industrial computers.
XA – Device suffix for automotive parts.
XNF File – Xilinx proprietary description format for a logic design Alternative: EDIF.
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Programmable Logic Design
June 12, 2006