DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 139

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
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PAL – Programmable Array Logic. Oldest practical form of programmable logic,
implemented a sum-of-products plus optional output flip-flops.
Partitioning – In FPGAs, the process of dividing the logic into sub-functions that can later
be placed into individual CLBs. Partitioning precedes placement.
PCI – Peripheral Component Interface. Synchronous bus standard characterized by short
range, light loading, low cost, and high performance. A 33 MHz PCI can support data byte
transfers of up to 132 megabytes per second on 36 parallel data lines (including parity) and
a common clock. There is also a new 66 MHz standard.
PCMCIA – Personal Computer Memory Card Interface Association. (Also: People Can’t
Memorize Computer Industry Acronyms). Physical and electrical standard for small plug-in
boards for portable computers.
Pin-Locking – Rigidly defining and maintaining the functionality and timing requirements
of device pins while the internal logic is still being designed or modified. Pin-locking has
become important, since circuit-board fabrication times are longer than PLD design
implementation times.
PIP – Programmable Interconnect Point. In Xilinx FPGAs, a point where two signal lines
can be connected, as determined by the device configuration.
Placement – In FPGAs, the process of assigning specific parts of the design to specific
locations (CLBs) on the chip. Usually done automatically.
PLA – Programmable Logic Array. The first and most flexible programmable logic
configuration with two programmable planes providing any combination of “AND” and “OR”
gates and sharing of AND terms across multiple ORs. This architecture is implemented in
CoolRunner and CoolRunner-II devices.
PLD – Programmable Logic Device. Most generic name for all programmable logic: PALs,
CPLDs, and FPGAs.
QML – Qualified Manufacturing Line. For example, ISO9000.
Routing – The interconnection, or the process of creating the desired interconnection, of
logic cells to make them perform the desired function. Routing follows partitioning and
placement.
Schematic – Graphic representation of a logic design in the form of interconnected gates,
flip-flops, and larger blocks. Older and more visually intuitive alternative to the increasingly
more popular equation-based or high-level language text description of a logic design.
SelectRAM – Xilinx-specific name for a small RAM (usually 16 bits), implemented in a LUT.
Simulation – Computer modeling of logic and (sometimes) timing behavior of logic driven
by simulation inputs (stimuli or vectors).
SPROM – Serial Programmable Read-Only Memory. Non-volatile memory device that can
store the FPGA configuration bitstream. The SPROM has a built-in address counter,
receives a clock, and outputs a serial bitstream.
SRAM – Static Random Access Memory. Read-write memory with data stored in latches.
Faster than DRAM and with simpler timing requirements, but smaller in size and about four
times as expensive than DRAM of the same capacity.
SRL16 – Shift Register LUT, an alternative mode of operation for every function generator
(LUT) that are part of every CLB in Virtex and Spartan FPGAs. This mode increases the
number of flip-flops by 16. Adding flip-flops enables fast pipelining – ideal in DSP
applications.
www.xilinx.com
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