DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 116

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 6: Implementing FPGA Designs
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6.
The first section of the report summarizes just the synthesis settings. Each entity in the
design is then compiled and analyzed. The next section in the report gives synthesis details
and documents how the design was interpreted. Note that the state machine is one hot
encoded, as each state name (red, amber, redamb, and green) has been assigned its own 1-
bit register.
Right-click on Synthesize - XST and select Properties.
A window will appear allowing you to influence the way in which your design is
interpreted.
Click on the HDL Options category.
The FSM encoding algorithm option looks for state machines and determines the best
method of optimizing. For FPGAs, state machines are usually “one-hot” encoded. This
is because of the abundance of flip-flops in FPGA architectures. A one-hot encoded
state machine will use one flip-flop per state. Although this may seem wasteful, the
next state logic is reduced, and the design is likely to run much faster. Leave the
setting on “auto” to achieve this fast one-hot encoding.
In the Xilinx Specific Options category, ensure that the Add I/O Buffers
box is checked as shown in
port names in the top-level entity of the design.
Clicking on Help in each category demonstrates the complex issue of synthesis and
how the final result could change.
Click OK in the Process Properties window, then double-click on Synthesize-
XST in the Process tree.
Figure 6-4: Two Synthesis Option Categories
www.xilinx.com
Figure
6-4. The I/O buffers will be attached to all of the
Programmable Logic Design
June 12, 2006
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