DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 16

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 1:
6
The dominant type of FPGA is SRAM-based and can be reprogrammed as often as you
choose. In fact, an SRAM FPGA is reprogrammed every time it’s powered up, because the
FPGA is really a fancy memory chip. That’s why you need a serial PROM or system
memory with every SRAM FPGA.
In the SRAM logic cell, instead of conventional gates, an LUT determines the output based
on the values of the inputs. (In the “SRAM logic cell” diagram above, six different
combinations of the four inputs determine the values of the output.) SRAM bits are also
used to make connections.
OTP FPGAs use anti-fuses (contrary to fuses, connections are made, not “blown,”
during programming) to make permanent connections in the chip. Thus, OTP FPGAs do
not require SPROM or other means to download the program to the FPGA. However,
every time you make a design change, you must throw away the chip! The OTP logic cell
is very similar to PLDs, with dedicated gates and flip-flops.
www.xilinx.com
Figure 1-6: SRAM Logic Cell
Figure 1-7: OTP Logic Cell
Programmable Logic Design
June 12, 2006
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