MC9S08QG4MPAE Freescale Semiconductor, MC9S08QG4MPAE Datasheet - Page 148

• Manufacturer Part Number: MC9S08QG4MPAE
• Description: IC MCU 4K FLASH 8-PDIP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG4MPAE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: HCS08
• No. Of I/o's: 6
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Internal Clock Source (S08ICSV1)
10.1.4.5
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
10.1.4.6
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
10.1.4.7
In stop mode, the FLL is disabled and the internal or external reference clock can be selected to be enabled
or disabled. The BDC clock is not available. ICS does not provide an MCU clock source.
10.1.5
This section contains the ICS block diagram.
146
Block Diagram
RANGE
FLL Bypassed Externa
FLL Bypassed Externa
Stop (STOP)
HGO
IREFS
Figure 10-2. Internal Clock Source (ICS) Block Diagram
External Reference
Clock Source
n=0-7
RDIV
/ 2
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Optional
Block
n
IREFSTEN
Reference
Internal
RDIV_CLK
TRIM
Clock
9
l (FBE)
l Low Power (FBELP)
EREFSTEN
EREFS
Filter
DCO
LP
FLL
ERCLKEN
IRCLKEN
9
Internal Clock Source Block
CLKS
DCOOUT
n=0-3
BDIV
/ 2
/ 2
n
ICSERCLK
ICSIRCLK
ICSOUT
ICSLCLK
ICSFFCLK
Freescale Semiconductor