MC9S08QG4MPAE Freescale Semiconductor, MC9S08QG4MPAE Datasheet - Page 238

• Manufacturer Part Number: MC9S08QG4MPAE
• Description: IC MCU 4K FLASH 8-PDIP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG4MPAE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: HCS08
• No. Of I/o's: 6
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Timer/Pulse-Width Modulator (S08TPMV2)
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
16.3.5
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
In input capture mode, reading either byte (TPMCnVH or TPMCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other byte is read. This latching mechanism also resets
(becomes unlatched) when the TPMCnSC register is written.
236
CPWMS
Reset
Reset
X
0
1
W
W
R
R
Bit 15
Timer Channel Value Registers (TPMCnVH:TPMCnVL)
Bit 7
0
0
7
7
MSnB:MSnA
XX
XX
1X
00
01
Figure 16-10. Timer Channel Value Register Low (TPMCnVL)
Figure 16-9. Timer Channel Value Register High (TPMCnVH)
14
0
6
0
6
6
ELSnB:ELSnA
Table 16-5. Mode, Edge, and Level Selection
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
X1
X1
00
01
10
11
00
01
10
11
10
10
13
0
5
0
5
5
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
Center-aligned
Edge-aligned
Input capture
compare
12
Output
Mode
PWM
PWM
0
4
0
4
4
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
High-true pulses (clear output on compare)
Low-true pulses (set output on compare)
High-true pulses (clear output on compare-up)
Low-true pulses (set output on compare-up)
11
3
0
3
3
0
10
0
2
0
2
2
Configuration
Freescale Semiconductor
9
0
1
0
1
1
Bit 8
Bit 0
0
0
0
0