MC9S08QG4MPAE Freescale Semiconductor, MC9S08QG4MPAE Datasheet - Page 154

• Manufacturer Part Number: MC9S08QG4MPAE
• Description: IC MCU 4K FLASH 8-PDIP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG4MPAE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: HCS08
• No. Of I/o's: 6
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Internal Clock Source (S08ICSV1)
times the filter frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for BDC
communications, and the external reference clock is enabled.
10.4.1.6
The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur:
In FLL bypassed external low power mode, the ICSOUT clock is derived from the external reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications. The external
reference clock is enabled.
10.4.1.7
ICS stop mode is entered whenever the MCU enters stop. In this mode, all ICS clock signals are stopped
except in the following cases:
ICSIRCLK will be active in stop mode when all the following conditions occur:
ICSERCLK will be active in stop mode when all the following conditions occur:
10.4.2
When switching between FLL engaged internal (FEI) and FLL engaged external (FEE) modes the IREFS
bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting
frequency stays in the range of 31.25 kHz to 39.0625 kHz. After a change in the IREFS value the FLL will
begin locking again after a few full cycles of the resulting divided reference frequency.
The CLKS bits can also be changed at anytime, but the RDIV bits must be changed simultaneously so that
the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. The actual switch to the newly
selected clock will not occur until after a few full cycles of the new clock. If the newly selected clock is
not available, the previous clock will remain selected.
10.4.3
The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur
immediately.
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CLKS bits are written to 10.
IREFS bit is written to 0.
BDM mode is not active and LP bit is written to 1.
IRCLKEN bit is written to 1
IREFSTEN bit is written to 1
ERCLKEN bit is written to 1
EREFSTEN bit is written to 1
Mode Switching
Bus Frequency Divider
FLL Bypassed External Low Power (FBELP)
Stop
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor