MC9S08QG4MPAE Freescale Semiconductor, MC9S08QG4MPAE Datasheet - Page 235

• Manufacturer Part Number: MC9S08QG4MPAE
• Description: IC MCU 4K FLASH 8-PDIP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG4MPAE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: HCS08
• No. Of I/o's: 6
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.3.2
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMCNTH or TPMCNTL) latches the contents of both bytes into a buffer where they
remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The coherency
mechanism is automatically restarted by an MCU reset, a write of any value to TPMCNTH or TPMCNTL,
or any write to the timer status/control register (TPMSC).
Reset clears the TPM counter registers.
Freescale Semiconductor
Reset
W
R
Bit 15
Timer Counter Registers (TPMCNTH:TPMCNTL)
1
2
0
7
The maximum frequency that is allowed as an external clock is one-fourth of the bus
frequency.
If the external clock input is shared with channel n and is selected as the TPM clock source,
the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try
to use the same pin for a conflicting function.
CLKSB:CLKSA
PS2:PS1:PS0
0:0
0:1
1:0
1:1
14
0
6
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Figure 16-4. Timer Counter Register High (TPMCNTH)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Table 16-2. TPM Clock Source Selection
Table 16-3. Prescale Divisor Selection
Any write to TPMCNTH clears the 16-bit counter.
13
0
5
TPM Clock Source to Prescaler Input
12
No clock selected (TPM disabled)
0
4
External source (TPMCLK)
Fixed system clock (XCLK)
Bus rate clock (BUSCLK)
TPM Clock Source Divided-By
11
3
0
128
16
32
64
1
2
4
8
Timer/Pulse-Width Modulator (S08TPMV2)
10
1,2
0
2
9
0
1
Bit 8
0
0
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