PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet
PIC18F86K22-I/PTRSL
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PIC18F86K22-I/PTRSL Summary of contents
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... Enhanced Flash Microcontrollers 2010 Microchip Technology Inc. PIC18F87K22 Family 64/80-Pin, High-Performance, with 12-Bit A/D and nanoWatt XLP Technology Preliminary Data Sheet DS39960B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F66K22 64K 32,768 PIC18F67K22 128K 65,536 PIC18F85K22 32K 16,383 PIC18F86K22 64K 32,768 PIC18F87K22 128K 65,536 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Special Microcontroller Features: • Operating Voltage Range: 1.8V to 5.5V • On-Chip 3.3V Regulator • Operating Speed MHz • ...
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... I C™ Master and Slave modes • Two Enhanced Addressable USART modules: - LIN/J2602 support - Auto-Baud Detect (ABD) • 12-Bit A/D Converter with Channels: - Auto-acquisition and Sleep operation - Differential input mode of operation • Integrated Voltage Reference Preliminary 2010 Microchip Technology Inc. ...
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... RF6/AN11/C1INA RF5/AN10/CV /C1INB REF RF4/AN9/C2INA RF3/AN8/C2INB/CTMUI RF2/AN7/C1OUT Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting and whether the device is in Microcontroller or Extended Microcontroller mode. 2: Not available on the PIC18F65K22 and PIC18F85K22 devices. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY ...
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... Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting and whether the device is in Microcontroller or Extended Microcontroller mode. 2: Not available on the PIC18F65K22 and PIC18F85K22 devices. 3: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). DS39960B-page PIC18F85K22 9 PIC18F86K22 10 11 PIC18F87K22 Preliminary RJ2/OE 60 RJ3/WRL 59 RB0/INT0/FLT0 58 ...
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... Appendix A: Revision History............................................................................................................................................................. 531 Appendix B: Migration From PIC18F87J11 and PIC18F8722 to PIC18F87K22................................................................................ 531 Index .................................................................................................................................................................................................. 533 The Microchip Web Site ..................................................................................................................................................................... 545 Customer Change Notification Service .............................................................................................................................................. 545 Customer Support .............................................................................................................................................................................. 545 Reader Response .............................................................................................................................................................................. 546 Product Identification System ............................................................................................................................................................ 547 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Preliminary DS39960B-page 7 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39960B-page 8 Preliminary 2010 Microchip Technology Inc. ...
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... This document contains device-specific information for the following devices: • PIC18F65K22 • PIC18F85K22 • PIC18F66K22 • PIC18F86K22 • PIC18F67K22 • PIC18F87K22 This family combines the traditional advantages of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – with an extremely competitive price point ...
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... CPU. • The module is a 100-year clock and calendar with automatic leap year detection. The range of the clock is from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099. Preliminary 2010 Microchip Technology Inc. ...
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... The devices are differentiated from each other in these ways: • Flash Program Memory: - PIC18FX5K22 (PIC18F65K22 and PIC18F85K22) – 32 Kbytes - PIC18FX6K22 (PIC18F66K22 and PIC18F86K22) – 64 Kbytes - PIC18FX7K22 (PIC18F67K22 and PIC18F87K22) – 128 Kbytes • Data RAM: - All devices except PIC18FX5K22 – 4 Kbytes - PIC18FX5K22 – 2 Kbytes • ...
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... Two MSSPs and two Enhanced USARTs (EUSART) 16 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 64-Pin QFN, 64-Pin TQFP PIC18F85K22 PIC18F86K22 DC – 64 MHz 32 K 64K ( Mbytes with Extended Memory) 16,384 32,768 ...
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... See Table 1-3 for I/O port pin descriptions. 2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator Configurations”. 3: Unimplemented on the PIC18F65K22. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Data Bus<8> Data Latch 8 8 ...
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... ADC CTMU (3) (3) /12 3/5/7 12-Bit RTCC MSSP1/2 EUSART2 Preliminary PORTA (1,2) RA0:RA7 PORTB (1) 12 RB0:RB7 4 PORTC Access Bank (1) RC0:RC7 12 PORTD (1) RD0:RD7 PORTE (1) RE0:RE7 8 PORTF PRODL (1) RF1:RF7 8 PORTG 8 8 (1) RG0:RG5 8 PORTH (1) 8 RH0:RH7 PORTJ (1) RJ0:RJ7 Comparator 1/2/3 2010 Microchip Technology Inc. ...
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... C™/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Buffer Type Type I ST Master Clear (input) or programming voltage (input). ...
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... I ST Timer1 clock input Timer3 external clock gate input. I Analog High/Low-Voltage Detect input. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... EUSART synchronous clock (see related RX1/DT1). I/O ST Digital I/ EUSART asynchronous receive. I/O ST EUSART synchronous data (see related TX1/CK1). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description 2 C™ mode 2010 Microchip Technology Inc. ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Buffer Type Type PORTD is a bidirectional I/O port. ...
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... ECCP1 PWM Output B. I/O S/T Capture 6 input/Compare 6 output/PWM6 output. I/O ST Digital I/O. I/O ST Capture 2 input/Compare 2 output/PWM2 output. O — ECCP2 PWM Output A. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Buffer Type Type PORTF is a bidirectional I/O port. ...
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... I/O ST Capture 5 input/Compare 5 output/PWM5 output. I Analog Analog Input 16. O — ECCP1 PWM Output D. I Analog Comparator 3 Input C. See the MCLR/RG5 pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... C™/SMBus Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Buffer Type Type P — Ground reference for logic and I/O pins. ...
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... In certain oscillator modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... External Memory Address Data 4. I/O ST Digital I/ SPI data in I C™ data I/O. I/O TTL Parallel Slave Port data. I/O TTL External Memory Address Data 5. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type I/O ST Digital I/O ...
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... TTL External Memory Address/Data 12. I/O ST Digital I/O. O — ECCP1 PWM Output C. I/O ST Capture 7 input/Compare 7 output/PWM7 output. I/O TTL External Memory Address/Data 13. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared. 3: Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type I/O ST Digital I/O ...
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... Comparator 1 Input B. I/O ST Digital I/O. I Analog Analog Input 11. I Analog Comparator 1 Input A. I/O ST Digital I/O. O Analog Analog Input SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. ...
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... Analog Input 14. I Analog Comparator 1 Input C. I/O ST Digital I/O. I/O ST Capture 6 input/Compare 6 output/PWM6 output. O — ECCP1 PWM Output B. I Analog Analog Input 15. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2010 Microchip Technology Inc. ...
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... Not available on PIC18F65K22 and PIC18F85K22 devices. 4: PSP is available only in Microcontroller mode. 5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit (CONFIG3H<1>). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port. ...
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... PIC18F87K22 FAMILY NOTES: DS39960B-page 36 Preliminary 2010 Microchip Technology Inc. ...
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... REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY FIGURE 2- MCLR C1 V (2) C6 ...
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... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC18FXXKXX JP C1 and V specifications are met and V specifications are met. IL 2010 Microchip Technology Inc. ...
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... These devices also do not have the ENVREG pin. The 10F capacitor is still required on the V /V pin. CAP DDCORE For details on all members of the PIC18F87K22 family, see Section 28.3 “On-Chip Voltage Regulator”. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY FIGURE 2-3: 10 enables DD 1 0.1 pin to DDCORE 0 ...
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... Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS Preliminary SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSC1 ` OSC2 GND ` T1OSO T1OS Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1 2010 Microchip Technology Inc. ...
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... When the RA6 and RA7 pins are not used for an oscil- lator function or CLKOUT function, they are available as general purpose I/Os. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY To optimize power consumption when using EC/HS/ XT/LP/RC as the primary oscillator, the frequency input ...
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... INTSRC MFIOSEL Preliminary FOSC<3:0> Setting 1101 1100 1011 1010 0101 0100 0011 0010 0001 0000 001x 100x (and OSCCON, OSCCON2) Peripherals CPU IDLEN Clock Control SCS<1:0> FOSC<3:0> IRCF<2:0> 2010 Microchip Technology Inc. ...
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... INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>. 6: Lowest power option for an internal source. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY The OSCTUNE register (Register 3-3) controls the tuning and operation of the internal oscillator block. It also implements the PLLEN bit which controls the operation of the Phase Locked Loop (PLL) (see Section 3.5.3 “ ...
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... MF-INTOSC is used in place of HF-INTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz 0 = MF-INTOSC is not used DS39960B-page 44 (1) (CONTINUED) (4) U-0 R/W-0 U-0 — SOSCGO — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary 2010 Microchip Technology Inc. R-x R/W-0 MFIOFS MFIOSEL bit Bit is unknown ...
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... Center frequency. Fast RC oscillator is running at the calibrated frequency. 111111 • • • • 100000 = Minimum frequency 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... The IDLEN bit (OSCCON<7>) determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. Preliminary 2010 Microchip Technology Inc. 31.25-100 kHz 100 kHz to 4 MHz 4 MHz to 25 MHz Select bits, SCS< ...
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... This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 “Entering Power-Managed Modes”. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 3.4 RC Oscillator For timing-insensitive applications, the RC and RCIO Oscillator modes offer additional cost savings ...
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... F Preliminary Typical Capacitor Values Tested this table for additional values of external and temperature range that is CRYSTAL/CERAMIC RESONATOR OPERATION (HS OR HSPLL CONFIGURATION) OSC1 To Internal Logic ( Sleep OSC2 PIC18F87K22 (2) ) may be required for AT S 2010 Microchip Technology Inc. ...
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... This may be useful for customers who are concerned with EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 3.5.3.1 HSPLL and ECPLL Modes The HSPLL and ECPLL modes provide the ability to ...
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... INTIO1 (Figure 3-8). • In INTPLL2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. Externally, this is identical to INTIO2 (Figure 3-9). Preliminary I/O (OSC1) PIC18F87K22 OSC2 I/O (OSC1) PIC18F87K22 I/O (OSC2) /4, OSC 2010 Microchip Technology Inc. ...
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... If the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 3.6.4.3 A CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i ...
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... For ROSEL (REVOCON<4>), the primary oscillator is available only when configured as the default via the FOSC settings. This is regardless of whether the device is in Sleep mode. DS39960B-page 52 R/W-0 R/W-0 R/W-0 (1) ROSEL RODIV3 RODIV2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 RODIV1 RODIV0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... I/O pin, RA6, direction controlled by TRISA<6> Note: See Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY The SOSC oscillator may be operating to support a Real-Time Clock (RTC). Other features may be operat- ing that do not require a device clock source (i.e., MSSP slave, INTx pins and others) ...
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... PIC18F87K22 FAMILY NOTES: DS39960B-page 54 Preliminary 2010 Microchip Technology Inc. ...
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... IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTOSC source. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source ...
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... Figure 4-2). When the clock switch is complete, the SOSCRUN bit is cleared, the OSTS bit is set and the . Improper DD primary clock is providing the clock. The IDLEN and / DD SCS bits are not affected by the wake-up and the SOSC oscillator continues to run. Preliminary 2010 Microchip Technology Inc. ...
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... HF-INTOSC) – there are no distinguishable differences between the PRI_RUN and RC_RUN modes during execution. Entering or exiting RC_RUN mode, how- ever, causes a clock switch delay. Therefore, if the primary clock source is the internal oscillator block, using RC_RUN mode is not recommended. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY n-1 ...
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... OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The LF-INTOSC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. Preliminary 2010 Microchip Technology Inc. ...
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... PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed Note1 1024 (approx). These intervals are not shown to scale. OST OSC PLL 2: Clock transition typically occurs within 2-4 T 2010 Microchip Technology Inc. PIC18F87K22 FAMILY n-1 n (1) Clock Transition OSC ...
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... IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time- out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits (1) T PLL OSTS bit Set Preliminary CSD 2010 Microchip Technology Inc. ...
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... OSC1 CPU Clock Peripheral Clock Program Counter Wake Event 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS< ...
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... PMD bit. There are four PMD registers in the PIC18F87K22 family devices: PMD0, PMD1, PMD2 and PMD3. These registers have bits associated with each module for disabling or enabling a particular peripheral. Preliminary 2010 Microchip Technology Inc. eliminating their power ...
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... RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence. Refer to Section 18.0 “Real-Time Clock and Calendar (RTCC)” for the unlock sequence (Example 18-1). 3: Unimplemented on devices with 64 pins (PIC18F6XK22). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 (1,3) ...
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... Clock and Calendar (RTCC)” for the unlock sequence (Example 18-1). 3: Unimplemented on devices with 64 pins (PIC18F6XK22). DS39960B-page 64 R/W-0 R/W-0 R/W-0 (1) TMR6MD TMR5MD CMP3MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,3) (1,3) (1) Preliminary (2) R/W-0 R/W-0 CMP2MD CMP1MD bit Bit is unknown 2010 Microchip Technology Inc. ...
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... RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence. Refer to Section 18.0 “Real-Time Clock and Calendar (RTCC)” for the unlock sequence (Example 18-1). 3: Unimplemented on devices with 64 pins (PIC18F6XK22). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 (1,2) ...
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... Clock and Calendar (RTCC)” for the unlock sequence (Example 18-1). 3: Unimplemented on devices with 64 pins (PIC18F6XK22). DS39960B-page 66 R/W-0 R/W-0 R/W-0 UART2MD UART1MD SSP2MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1,2,3) R/W-0 R/W-0 SSP1MD ADCMD bit Bit is unknown 2010 Microchip Technology Inc. ...
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... WDT timer and postscaler, loses the currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifies the IRCF bits in the OSCCON register (if the internal oscillator block is the device clock source). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 4.6.3 EXIT BY RESET ...
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... The peripheral can also be configured as a simple Programmable Low-Voltage Detect (LVD) or temperature sensor. Note: For more information, see AN879, “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879). Preliminary ULTRA LOW-POWER WAKE-UP INITIALIZATION 2010 Microchip Technology Inc. ...
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... OST (parameter F12, Table 31-7 also designated Execution continues during T 5: The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>) and FOSC (CONFIG1H<3:0>) bits. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY (5) Clock Source Exit Delay LP, XT, HS HSPLL EC, RC ...
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... PIC18F87K22 FAMILY NOTES: DS39960B-page 70 Preliminary 2010 Microchip Technology Inc. ...
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... Reset PWRT 32 s PWRT 11-Bit Ripple Counter LF-INTOSC 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39960B-page 72 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 POR BOR bit Bit is unknown 2010 Microchip Technology Inc. ...
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... SBOREN bit (RCON<6>). The typical current draw (I ) for zero, low and medium power BOR is BOR 200 nA, 750 nA and 3 A, respectively. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY In Zero-Power BOR (ZPBORMV), the module monitors the V voltage and re-arms the POR at about 2V. ...
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... MCLR is kept low long enough, the PWRT will expire. Bringing MCLR high will begin execution immediately (Figure 5-5). This is useful for testing purposes, or for synchronizing more than one PIC18 device operating in parallel PWRT Preliminary 2010 Microchip Technology Inc. all depict time-out , V RISE < PWRT ...
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... FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F87K22 FAMILY T PWRT T PWRT , V RISE > 3. PWRT Preliminary ...
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... Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets, and WDT wake-ups. RCON Register ( POR Preliminary STKPTR Register BOR STKFUL STKUNF 2010 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, ...
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... PIC18F6XK22 PIC18F8XK22 TMR0H PIC18F6XK22 PIC18F8XK22 TMR0L PIC18F6XK22 PIC18F8XK22 T0CON PIC18F6XK22 PIC18F8XK22 SPBRGH1 PIC18F6XK22 PIC18F8XK22 OSCCON PIC18F6XK22 PIC18F8XK22 IPR5 PIC18F65K22 PIC18F85K22 PIC18F66K22 PIC18F86K22 IPR5 PIC18F67K22 PIC18F87K22 WDTCON PIC18F6XK22 PIC18F8XK22 RCON PIC18F6XK22 PIC18F8XK22 TMR1H PIC18F6XK22 PIC18F8XK22 TMR1L PIC18F6XK22 PIC18F8XK22 T1CON PIC18F6XK22 PIC18F8XK22 TMR2 ...
Page 79
... PIC18F66K22 PIC18F86K22 IPR4 PIC18F67K22 PIC18F87K22 PIR4 PIC18F65K22 PIC18F85K22 PIC18F66K22 PIC18F86K22 PIR4 PIC18F67K22 PIC18F87K22 PIE4 PIC18F65K22 PIC18F85K22 PIC18F66K22 PIC18F86K22 PIE4 PIC18F67K22 PIC18F87K22 CVRCON PIC18F6XK22 PIC18F8XK22 CMSTAT PIC18F6XK22 PIC18F8XK22 TMR3H PIC18F6XK22 PIC18F8XK22 TMR3L PIC18F6XK22 PIC18F8XK22 T3CON PIC18F6XK22 PIC18F8XK22 T3GCON PIC18F6XK22 PIC18F8XK22 SPBRG1 PIC18F6XK22 PIC18F8XK22 ...
Page 80
... Preliminary 2010 Microchip Technology Inc. Wake-up via WDT or Interrupt u-uu uuuu u-uu uuuu u-uu uuuu u-uu uuuu u-uu uuuu u-uu uuuu uuuu uuuu uuuu uuuu ...
Page 81
... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, ...
Page 82
... PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 CCPR10H PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 CCPR10L PIC18F67K22 PIC18F87K22 Legend unchanged unknown unimplemented bit, read as ‘0’ value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC ...
Page 83
... PIC18F6XK22 PIC18F8XK22 T8CON PIC18F6XK22 PIC18F8XK22 PIC18F66K22 PIC18F86K22 TMR10 PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 PR10 PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 T10CON PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 TMR12 PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 PR12 PIC18F67K22 PIC18F87K22 PIC18F66K22 PIC18F86K22 T12CON PIC18F67K22 PIC18F87K22 CM2CON PIC18F6XK22 PIC18F8XK22 CM3CON PIC18F6XK22 PIC18F8XK22 CCPTMRS0 ...
Page 84
... PMD1 PIC18F6XK22 PIC18F8XK22 PIC18F66K22 PIC18F86K22 PMD2 PIC18F67K22 PIC18F87K22 PMD2 PIC18F65K22 PIC18F85K22 PIC18F66K22 PIC18F86K22 PMD3 PIC18F67K22 PIC18F87K22 PMD3 PIC18F65K22 PIC18F85K22 Legend unchanged unknown unimplemented bit, read as ‘0’ value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC ...
Page 85
... Unimplemented Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY The data EEPROM, for practical purposes, can be regarded as a peripheral device because it is addressed and accessed through a set of control registers ...
Page 86
... PIC18F65K22 and PIC18F85K22 – 32 Kbytes of Flash memory, storing up to 16,384 single-word instructions • PIC18F66K22 and PIC18F86K22 – 64 Kbytes of Flash memory, storing up to 32,768 single-word instructions • PIC18F67K22 and PIC18F87K22 – 128 Kbytes of Flash memory, storing up to 65,536 single-word ...
Page 87
... TOSH TOSL 00h 1Ah 34h 2010 Microchip Technology Inc. PIC18F87K22 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
Page 88
... TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary and Instructions POP R/W-0 R/W-0 SP1 SP0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 89
... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 6.1.5 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
Page 90
... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Fetch INST ( Execute INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Preliminary Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 2010 Microchip Technology Inc. ...
Page 91
... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF 2010 Microchip Technology Inc. PIC18F87K22 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
Page 92
... When this instruction executes, it ignores the BSR completely. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Preliminary 2010 Microchip Technology Inc. ...
Page 93
... BSR value, to access these registers. 2: These addresses are unused for devices with 32 Kbytes of program memory (PIC18FX5K22). For those devices, read these addresses at 00h. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Data Memory Map ...
Page 94
... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Preliminary (2) From Opcode 2010 Microchip Technology Inc. ...
Page 95
... Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. To access these registers, users must always load the proper BSR value. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY The SFRs can be classified into two sets: those associated with the “ ...
Page 96
... INT0IF RBIF 0000 000x INT3IP RBIP 1111 1111 INT2IF INT1IF 1100 0000 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- xxxx xxxx xxxx xxxx xxxx ---- ---- 2010 Microchip Technology Inc. ...
Page 97
... Note 1: The bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK22). 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Bit 5 Bit 4 Bit 3 — — Indirect Data Memory Address Pointer 1 High — ...
Page 98
... LATE2 LATE1 LATE0 xxxx xxxx LATD2 LATD1 LATD0 xxxx xxxx LATC2 LATC1 LATC0 xxxx xxxx LATB2 LATB1 LATB0 xxxx xxxx LATA2 LATA1 LATA0 xxxx xxxx RJ2 RJ1 RJ0 xxxx xxxx RH2 RH1 RH0 xxxx xxxx 2010 Microchip Technology Inc. ...
Page 99
... RTCC Value High Register Window Based on RTCPTR<1:0> Note 1: The bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK22). 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RG5 RG4 ...
Page 100
... T8CKPS1 T8CKPS0 -000 0000 0000 0000 1111 1111 T10CKPS1 T10CKPS0 -000 0000 0000 0000 1111 1111 T12CKPS1 T12CKPS0 -000 0000 CCH1 CCH0 0001 1111 CCH1 CCH0 0001 1111 C1TSEL1 C1TSEL0 0000 0000 2010 Microchip Technology Inc. ...
Page 101
... CCP9MD Note 1: The bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented. 2: Unimplemented on 64-pin devices (PIC18F6XK22). 3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Bit 5 Bit 4 Bit 3 — C6TSEL0 — ...
Page 102
... Table 29-2 and Table 29-3. Note: The C and DC bits operate, in subtraction, as borrow and digit borrow bits, respectively. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-x R/W-x (1) ( bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 103
... Least Significant Byte. This address specifies the instruction’s data source as either a register address in one of the banks 2010 Microchip Technology Inc. PIC18F87K22 FAMILY of data RAM (see Section 6.3.3 “General Purpose Register File” location in the Access Bank (see Section 6.3.2 “ ...
Page 104
... RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. ADDWF, INDF1, 1 FSR1H:FSR1L Preliminary 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory 2010 Microchip Technology Inc. ...
Page 105
... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases ...
Page 106
... Figure 6-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 29.2.1 “Extended Instruction Syntax”. Preliminary 2010 Microchip Technology Inc. ...
Page 107
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 000h 060h Bank 0 100h Bank 1 through ...
Page 108
... BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. Not Accessible Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Preliminary 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank 2010 Microchip Technology Inc. ...
Page 109
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 110
... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR6<4>) is set when the write is complete. It must be cleared in software. When set, Preliminary Table Latch (8-bit) TABLAT 2010 Microchip Technology Inc. ...
Page 111
... The RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-x R/W-0 ...
Page 112
... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> Preliminary TBLPTRL 0 TABLE WRITE TBLPTR<5:0> 2010 Microchip Technology Inc. ...
Page 113
... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD 2010 Microchip Technology Inc. PIC18F87K22 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, the TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 114
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary 2010 Microchip Technology Inc. ...
Page 115
... TABLE WRITES TO FLASH PROGRAM MEMORY 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 Holding Register 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 64 or 128 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. The long write is necessary for programming the internal Flash ...
Page 116
... Note: Self-write execution EEPROM memory cannot be done while running in LP Oscillator mode (Low-Power mode). Therefore, executing a self-write will put the device into High-Power mode. IW Preliminary 2010 Microchip Technology Inc. to Flash and ...
Page 117
... MOVFF POSTINC0, WREG MOVWF TABLAT TBLWT+* DECFSZ COUNTER BRA WRITE_BYTE_TO_HREGS 2010 Microchip Technology Inc. PIC18F87K22 FAMILY ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block ; read into TABLAT, and inc ; get data ; store data ...
Page 118
... Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) INT0IE RBIE — FREE WRERR — EEIP — — EEIF — — EEIE — Preliminary Bit 2 Bit 1 Bit 0 TMR0IF INT0IF RBIF WREN WR RD CMP3IP CMP2IP CMP1IP CMP3IF CMP2IF CMP1IF CMP3IE CMP2IE CMP1IE 2010 Microchip Technology Inc. ...
Page 119
... Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
Page 120
... Data Width Modes”. These bits have no effect when an 8-Bit Data Width mode is selected. R/W-0 U-0 U-0 WAIT0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 WM1 WM0 bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 121
... Microchip Technology Inc. PIC18F87K22 FAMILY 8.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS By default, the address presented on the external bus is the value of the PC. In practical terms, this means that addresses in the external memory device below the top of on-chip memory are unavailable to the micro- controller ...
Page 122
... BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the signals for byte selection. Preliminary 2010 Microchip Technology Inc. the MEMCON register ...
Page 123
... Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD< ...
Page 124
... A<20:1> 373 D<15:0> 373 Preliminary cycle to an odd address JEDEC Word A<x:0> EPROM Memory D<15:0> ( Address Bus Data Bus Control Lines 2010 Microchip Technology Inc. ...
Page 125
... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 126
... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Preliminary Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive 2010 Microchip Technology Inc. ...
Page 127
... This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
Page 128
... TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 3Ah 55h ABh 0Eh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Preliminary Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive 2010 Microchip Technology Inc. ...
Page 129
... PMD1 PSPMD CTMUMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during external memory bus access. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended ...
Page 130
... PIC18F87K22 FAMILY NOTES: DS39960B-page 130 Preliminary 2010 Microchip Technology Inc. ...
Page 131
... EEPROM for read and write operations. EEADRH holds the two MSbs of the address; the upper 6 bits are ignored. The 10-bit range of the pair can address a memory range of 1024 bytes (00h to 3FFh). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 9.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2 ...
Page 132
... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39960B-page 132 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/S-0 R/S bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 133
... The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY After a write sequence has been initiated, EECON1, EEADRH:EEADR and EEDATA cannot be modified. ...
Page 134
... Data Memory Value to write ; Point to DATA memory ; Access EEPROM ; Enable writes ; Disable Interrupts ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete GOTO $-2 ; Enable Interrupts ; User code execution ; Disable writes on write complete (EEIF set) Preliminary 2010 Microchip Technology Inc. ...
Page 135
... LOOP INCFSZ EEADRH, F BRA LOOP BCF EECON1, WREN BSF INTCON, GIE 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 9.8 Using the Data EEPROM The data EEPROM is a high-endurance, byte address- and write able array that has been optimized for the storage of ...
Page 136
... Bit 5 Bit 4 Bit 3 TMR0IE INT0IE RBIE TMR0IF — FREE WRERR WREN — EEIP — CMP3IP — EEIF — CMP3IF — EEIE — CMP3IE Preliminary Bit 2 Bit 1 Bit 0 INT0IF RBIF WR RD CMP2IP CMP1IP CMP2IF CMP1IF CMP2IE CMP1IE 2010 Microchip Technology Inc. ...
Page 137
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2010 Microchip Technology Inc. PIC18F87K22 FAMILY EXAMPLE 10-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 10-2: MOVF ARG1, W MULWF ARG2 BTFSC ...
Page 138
... RES2 WREG ; RES3 ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products RES2 WREG ; RES3 ARG2H ARG2H:ARG2L neg? ; no, check ARG1 ARG1L RES2 ; ARG1H RES3 ; ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H RES3 2010 Microchip Technology Inc. ...
Page 139
... Individual interrupts can be disabled through their corresponding enable bits. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 140
... PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Preliminary 2010 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 141
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction cycle, will end the mismatch condition and allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Note: Interrupt flag bits are set when an interrupt ...
Page 142
... This feature allows for software polling. DS39960B-page 142 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 143
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 ...
Page 144
... R-0 R/W-0 R/W-0 TX1IF SSP1IF TMR1GIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 145
... TMR3 register overflowed (bit must be cleared in software TMR3 register did not overflow bit 0 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (bit must be cleared in software timer gate interrupt occurred 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 BCL2IF ...
Page 146
... RTCCIF: RTCC Interrupt Flag bit 1 = RTCC interrupt occured (must be cleared in software RTCC interrupt occured DS39960B-page 146 R-0 R/W-0 R/W-0 TX2IF CTMUIF CCP2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CCP1IF RTCCIF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 147
... Compare Mode TMR register compare match occurred (must be cleared in software TMR register compare match occurred PWM Mode: Not used in PWM mode. Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 CCP7IF CCP6IF CCP5IF U = Unimplemented bit, read as ‘ ...
Page 148
... Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). DS39960B-page 148 R/W-0 R/W-0 R/W-0 (1) (1) TMR8IF TMR7IF TMR6IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) Preliminary R/W-0 R/W-0 TMR5IF TMR4IF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 149
... CMP2IF: CMP2 Interrupt Flag bit 1 = CMP2 interrupt occurred (must be cleared in software CMP2 interrupt occurred bit 0 CMP1IF: CM1 Interrupt Flag bit 1 = CMP1 interrupt occurred (must be cleared in software CMP1 interrupt occurred 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 U-0 R/W-0 EEIF — ...
Page 150
... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS39960B-page 150 R/W-0 R/W-0 R/W-0 TX1IE SSP1IE TMR1GIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 151
... Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 BCL2IE BCL1IE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 152
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CCP7IE CCP6IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 CCP1IE RTCCIE bit Bit is unknown R/W-0 R/W-0 CCP4IE CCP3IE bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 153
... Disables the TMR5 overflow interrupt bit 0 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 match interrupt 0 = Disables the TMR4 to PR4 match interrupt Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-0 R/W-0 R/W-0 (1) (1) ...
Page 154
... CMP1IE: CMP1 Enable bit 1 = Interrupt is enabled 0 = interrupt is disabled DS39960B-page 154 R/W-0 U-0 R/W-0 EEIE — CMP3IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CMP2IE CMP1IE bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 155
... TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-1 R/W-1 R/W-1 TX1IP SSP1IP TMR1GIP U = Unimplemented bit, read as ‘0’ ...
Page 156
... TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority DS39960B-page 156 R/W-1 R/W-1 R/W-1 BCL2IP BCL1IP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR3IP TMR3GIP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 157
... Bit is set bit 7-0 CCP<10:3>IP: CCP<10:3> Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: CCP10IP and CCP9IP are unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R-1 R/W-1 R/W-1 TX2IP CTMUIP CCP2IP U = Unimplemented bit, read as ‘ ...
Page 158
... Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22). DS39960B-page 158 R/W-1 R/W-1 R/W-1 (1) (1) TMR8IP TMR7IP TMR6IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) (1) Preliminary R/W-1 R/W-1 TMR5IP TMR4IP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 159
... Low priority bit 1 CMP2IP: CMP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CMP1IP: CMP1 Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F87K22 FAMILY R/W-1 U-0 R/W-1 EEIE — CMP3IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 160
... For details of bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. DS39960B-page 160 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 POR BOR bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 161
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 11.7 TMR0 Interrupt In 8-bit mode (the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh ...
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... TMR1IE HLVDIE TMR3IE TMR3GIE CCP2IE CCP1IE RTCCIE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE CMP3IE CMP2IE CMP1IE TMR1GIP TMR2IP TMR1IP HLVDIP TMR3IP TMR3GIP CCP2IP CCP1IP RTCCIP CCP5IP CCP4IP CCP3IP TMR6IP TMR5IP TMR4IP CMP3IE CMP2IE CMP1IE PD POR BOR 2010 Microchip Technology Inc. ...
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... TRIS Latch RD TRIS PORT 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 12.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V All of the digital ports are 5.5V input tolerant. The ana- log ports have the same tolerance – ...
Page 164
... To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set. 2: Available only in 80-pin parts. DS39960B-page 164 U-0 U-0 R/W-0 (1) — — RTSECSEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) Preliminary R/W-0 U-0 (1) RTSECSEL0 — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 165
... Open-drain capability enabled 0 = Open-drain capability disabled bit 4-1 Unimplemented: Read as ‘0’ bit 0 SSP2OD: MSSP2 Open-Drain Output Enable bit 1 = Open-drain capability enabled 0 = Open-drain capability disabled 2010 Microchip Technology Inc. PIC18F87K22 FAMILY FIGURE 12-2: USING THE OPEN-DRAIN OUTPUT (USART SHOWN AS EXAMPLE) 3.3V PIC18F87K22 ...
Page 166
... Open-drain capability disabled Note 1: Not implemented on devices with 32-byte program memory (PIC18FX5K22). DS39960B-page 166 R/W-0 R/W-0 R/W-0 CCP7OD CCP6OD CCP5OD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 R/W-0 CCP4OD CCP3OD bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 167
... PIC18F87K22 family devices can make any analog pin analog or digital, depending on an application’s needs. The ports’ analog/digital functionality is controlled by the registers: ANCON0, ANCON1 and ANCON2. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY U-0 U-0 U-0 — ...
Page 168
... Select bank with ANCON1 register MOVLW 00h ; Configure A/D MOVWF ANCON1 ; for digital inputs BANKSEL TRISA ; Select bank with TRISA register MOVLW 0BFh ; Value used to initialize ; data direction MOVWF TRISA ; Set RA<7, 5:0> as inputs, ; RA<6> as output Preliminary 2010 Microchip Technology Inc. OSC1/CLKI/RA7 normally ...
Page 169
... Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘x’. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY I/O I/O ...
Page 170
... PORTB<1> data input; weak pull-up when RBPU bit is cleared External Interrupt 1 input. O DIG LATB<2> data output. I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared External Interrupt 2 input CTMU Edge 1 input. Preliminary can wake the device from delay. CY Description 2010 Microchip Technology Inc. ...
Page 171
... PEIE/GIEL INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP ODCON1 SSP1OD CCP2OD Legend: Shaded cells are not used by PORTB. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY I/O I/O Type O DIG LATB<3> data output. I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared External Interrupt 3 input ...
Page 172
... May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. Preliminary INITIALIZING PORTC ; Initialize PORTC by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs 2010 Microchip Technology Inc. ...
Page 173
... TRISC TRISC7 TRISC6 ODCON1 SSP1OD CCP2OD ODCON3 U2OD U1OD Legend: Shaded cells are not used by PORTC. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY I/O Description Type DIG LATC<3> data output. ST PORTC<3> data input. DIG SPI clock output (MSSP module); takes priority over port data. ...
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... TTL External Memory Address/Data 2. Preliminary 2 C and SPI functionality on INITIALIZING PORTD ; Initialize PORTD by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Description 2010 Microchip Technology Inc. ...
Page 175
... TRISD TRISD7 TRISD6 PADCFG1 RDPU REPU ODCON1 SSP1OD CCP2OD Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on PIC18F6XK22 devices, read as ‘0’. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY I/O I/O Type O DIG LATD<3> data output PORTD<3> data input. I/O TTL Parallel Slave Port data ...
Page 176
... External memory interface, Data Bit 9 output. I TTL External memory interface, Data Bit 9 input. Preliminary INITIALIZING PORTE ; Initialize PORTE by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RE<1:0> as inputs ; RE<7:2> as outputs Description 2010 Microchip Technology Inc. ...
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... Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode. 2: This feature is only available on PIC18F8XKXX devices. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY I/O I/O Type ...
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... LATE3 TRISE5 TRISE4 TRISE3 — — — RTSECSEL1 RTSECSEL0 CCP1OD — — CCP8OD CCP7OD CCP6OD Preliminary Description Bit 2 Bit 1 Bit 0 RE2 RE1 RE0 LATE2 LATE1 LATE0 TRISE2 TRISE1 TRISE0 — — — SSP2OD CCP5OD CCP4OD CCP3OD 2010 Microchip Technology Inc. ...
Page 179
... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY EXAMPLE 12-6: ...
Page 180
... Bit 3 RF5 RF4 RF3 LATF5 LATF4 LATF3 TRISF5 TRISF4 TRISF3 ANSEL5 ANSEL4 ANSEL3 ANSEL13 ANSEL12 ANSEL11 Preliminary Description Bit 2 Bit 1 Bit 0 RF2 RF1 — LATF2 LATF1 — TRISF2 TRISF1 — ANSEL2 ANSEL1 ANSEL0 ANSEL10 ANSEL9 ANSEL8 2010 Microchip Technology Inc. ...
Page 181
... Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin ...
Page 182
... TRISG3 ANSEL21 ANSEL20 ANSEL19 CCP1OD — — (1) CCP8OD CCP7OD CCP6OD — — — Preliminary Description Bit 2 Bit 1 Bit 0 RG2 RG1 RG0 TRISG2 TRISG1 TRISG0 ANSEL18 ANSEL17 ANSEL16 — — SSP2OD CCP5OD CCP4OD CCP3OD — — CTMUDS 2010 Microchip Technology Inc. ...
Page 183
... C2INC x Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87K22 FAMILY EXAMPLE 12-8: CLRF PORTH CLRF ...
Page 184
... LATH3 TRISH5 TRISH4 TRISH3 ANSEL13 ANSEL12 ANSEL11 ANSEL21 ANSEL20 ANSEL19 CCP8OD CCP7OD CCP6OD Preliminary Description Bit 2 Bit 1 Bit 0 RH2 RH1 RH0 LATH2 LATH1 LATH0 TRISH2 TRISH1 TRISH0 ANSEL10 ANSEL9 ANSEL8 ANSEL18 ANSEL17 ANSEL16 CCP5OD CCP4OD CCP3OD 2010 Microchip Technology Inc. ...
Page 185
... EBDIS (MEMCON<7>). The TRISJ bits are also overridden. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Each of the PORTJ pins has a weak internal pull-up. The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up. A single control bit can turn off all the pull-ups. This is performed by clearing bit RJPU (PADCFG1< ...
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... I/O. Bit 5 Bit 4 Bit 3 RJ5 RJ4 RJ3 LATJ5 LATJ4 LATJ3 TRISJ5 TRISJ4 TRISJ3 (1) RJPU — — RTSECSEL1 RTSECSEL0 Preliminary Description Bit 2 Bit 1 Bit 0 RJ2 RJ1 RJ0 LATJ2 LATJ1 LATJ0 TRISJ2 TRISJ1 TRISJ0 — 2010 Microchip Technology Inc. ...
Page 187
... PSP. When this happens, the IBF and OBF bits can be polled and the appropriate action taken. The timing for the control signals in Write and Read modes is shown in Figure 12-4 and Figure 12-5, respectively. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY FIGURE 12-3: Data Bus D WR LATD ...
Page 188
... FIGURE 12-4: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF DS39960B-page 188 R/W-0 U-0 PSPMODE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 U-0 — — — bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 189
... PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PMD1 PSPMD CTMUMD Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Bit 5 Bit 4 Bit 3 RD5 RD4 RD3 LATD5 ...
Page 190
... PIC18F87K22 FAMILY NOTES: DS39960B-page 190 Preliminary 2010 Microchip Technology Inc. ...
Page 191
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F87K22 FAMILY The T0CON register (Register 13-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. Figure 13-1 provides a simplified block diagram of the Timer0 module in 8-bit mode ...
Page 192
... Sync with TMR0L Internal Clocks Delay Preliminary ). There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 193
... GIE/GIEH PEIE/GIEL T0CON TMR0ON T08BIT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY 13.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F87K22 FAMILY NOTES: DS39960B-page 194 Preliminary 2010 Microchip Technology Inc. ...
Page 195
... Note 1: The F clock source should not be selected if the timer will be used with the ECCP capture/compare features. OSC 2010 Microchip Technology Inc. PIC18F87K22 FAMILY Figure 14-1 displays a simplified block diagram of the Timer1 module. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation ...
Page 196
... Timer1 gate pin Note 1: Programming the T1GCON prior to T1CON is recommended. DS39960B-page 196 (T1GCON), (1) R/W-0 R/W-0 R-x T1GVAL T1GSPM T1GGO/T1DONE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 T1GSS1 T1GSS0 bit Bit is unknown 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F87K22 FAMILY 14.3.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input, T1CKI. Either of these external clock sources can be synchronized to the ...
Page 198
... Q D TMR1CS<1:0> T1SYNC (4) 10 Prescaler OSC Internal 01 0 T1CKPS<1:0> Clock F /4 OSC Internal 00 Clock (1) Preliminary 0 Data Bus T1GVAL T1GCON Q1 EN Interrupt Set TMR1GIF det TMR1GE Synchronized 0 Clock Input 1 (3) Synchronize det OSC Sleep Input Internal Clock 2010 Microchip Technology Inc. ...
Page 199
... Figure 14-2. Table 14-2 provides the capacitor selection for the SOSC oscillator. The user must provide a software time delay to ensure proper start-up of the SOSC oscillator. 2010 Microchip Technology Inc. PIC18F87K22 FAMILY FIGURE 14-2: EXTERNAL COMPONENTS FOR THE SOSC ...
Page 200
... Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, . TMR1IE (PIE1<0>). Preliminary OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING OSC1 OSC2 RC0 RC1 RC2 2010 Microchip Technology Inc. ...