PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 187

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.11 Parallel Slave Port
PORTD can function as an 8-bit-wide Parallel Slave
Port (PSP), or microprocessor port, when control bit,
PSPMODE (PSPCON<4>), is set. The port is asyn-
chronously readable and writable by the external world
through the RD control input pin (RE0/P2D/RD/AD8)
and WR control input pin (RE1/P2C/WR/AD9).
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an eight-bit latch.
Setting
RE0/P2D/RD/AD8,
RE1/P2C/WR/AD9
RE2/P2B/CCP10/CS/AD10 to be the CS (Chip Select)
input. For this functionality, the corresponding data
direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (= 111).
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits (PIR1<7>
and PSPCON<7>, respectively) are set when the write
ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit (PSPCON<6>) is set. If the user
writes new data to PORTD to set OBF, the data is
immediately read out, but the OBF bit is not set.
When either the CS or RD line is detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in Figure 12-4 and Figure 12-5,
respectively.
 2010 Microchip Technology Inc.
Note:
bit,
The Parallel Slave Port is available only in
Microcontroller mode.
PSPMODE,
to
to
be
be
the
enables
the
WR
RD
input
port
input,
pin,
and
Preliminary
PIC18F87K22 FAMILY
FIGURE 12-3:
Note: The I/O pin has protection diodes to V
One Bit of PORTD
Data Bus
Set Interrupt Flag
PSPIF (PIR1<7>)
WR LATD
or
PORTD
RD PORTD
RD LATD
Data Latch
TRIS Latch
Q
D
CK
EN
EN
Q
D
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Chip Select
Read
Write
DS39960B-page 187
TTL
TTL
TTL
TTL
DD
and V
RDx
Pin
RD
CS
WR
SS
.