PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 542

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
Special Event Trigger. See Compare (ECCP Mode).
SPI Mode (MSSP)............................................................. 279
SSPOV.............................................................................. 315
SSPOV Status Flag........................................................... 315
SSPxSTAT Register
SSx.................................................................................... 279
Stack Full/Underflow Resets ............................................... 89
SUBFSR............................................................................ 475
SUBFWB........................................................................... 464
SUBLW ............................................................................. 465
SUBULNK ......................................................................... 475
SUBWF ............................................................................. 465
SUBWFB........................................................................... 466
SWAPF ............................................................................. 466
T
Table Pointer Operations (table) ....................................... 112
Table Reads/Table Writes................................................... 89
TBLRD .............................................................................. 467
TBLWT .............................................................................. 468
Timer0 ............................................................................... 191
Timer1 ............................................................................... 195
DS39960B-page 542
Associated Registers ................................................ 288
Bus Mode Compatibility ............................................ 287
Clock Speed, Interactions ......................................... 287
Effects of a Reset...................................................... 287
Enabling SPI I/O ....................................................... 283
Master Mode ............................................................. 284
Master/Slave Connection .......................................... 283
Operation .................................................................. 282
Operation in Power-Managed Modes ....................... 287
Serial Clock............................................................... 279
Serial Data In ............................................................ 279
Serial Data Out ......................................................... 279
Slave Mode ............................................................... 285
Slave Select .............................................................. 279
Slave Select Synchronization ................................... 285
SPI Clock .................................................................. 284
SSPxBUF Register ................................................... 284
SSPxSR Register...................................................... 284
Typical Connection ................................................... 283
R/W Bit .............................................................. 294, 297
Associated Registers ................................................ 193
Operation .................................................................. 192
Overflow Interrupt ..................................................... 193
Prescaler ................................................................... 193
Prescaler Assignment (PSA Bit) ............................... 193
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 193
Reads and Writes in 16-Bit Mode ............................. 192
Source Edge Select (T0SE Bit)................................. 192
Source Select (T0CS Bit) .......................................... 192
16-Bit Read/Write Mode............................................ 199
Associated Registers ................................................ 205
Clock Source Selection ............................................. 197
Gate .......................................................................... 201
Interrupt..................................................................... 200
Operation .................................................................. 197
Oscillator ................................................................... 195
Oscillator, as Secondary Clock ................................... 46
Resetting, Using the ECCP Special
SOSC Oscillator ........................................................ 199
TMR1H Register ....................................................... 195
TMR1L Register ........................................................ 195
Switching Assignment....................................... 193
SOSC Layout Considerations ........................... 200
Event Trigger .................................................... 201
Preliminary
Timer2............................................................................... 207
Timer3/5/7......................................................................... 209
Timer4
Timer4/6/8/10/12............................................................... 221
Timing Diagrams
Using SOSC as a Clock Source ............................... 200
Associated Registers ................................................ 208
Interrupt .................................................................... 208
Operation .................................................................. 207
Output ....................................................................... 208
PR2 Register ............................................................ 253
TMR2 to PR2 Match Interrupt................................... 253
16-Bit Read/Write Mode ........................................... 214
Associated Registers ................................................ 220
Gates ........................................................................ 215
Operation .................................................................. 213
Oscillator................................................................... 209
Overflow Interrupt ............................................. 209, 219
Special Event Trigger (ECCP) .................................. 219
TMRxH Register ....................................................... 209
TMRxL Register........................................................ 209
Using SOSCO Oscillator as Clock Source ............... 214
MSSP Clock Shift ..................................................... 222
Associated Registers ................................................ 223
Interrupt .................................................................... 222
Operation .................................................................. 221
Output ....................................................................... 222
Postscaler. See Postscaler, Timer4/6/8/10/12.
Prescaler. See Prescaler, Timer4/6/8/10/12.
PRx Register............................................................. 221
TMRx Register.......................................................... 221
A/D Conversion......................................................... 521
Asynchronous Reception.......................................... 339
Asynchronous Transmission..................................... 336
Asynchronous Transmission (Back-to-Back)............ 336
Automatic Baud Rate Calculation ............................. 334
Auto-Wake-up Bit (WUE) During Normal
Auto-Wake-up Bit (WUE) During Sleep .................... 341
Baud Rate Generator with Clock Arbitration............. 312
BRG Overflow Sequence.......................................... 334
BRG Reset Due to SDAx Arbitration During
Brown-out Reset (BOR)............................................ 507
Bus Collision During Repeated Start
Bus Collision During Repeated Start
Bus Collision During Start Condition
Bus Collision During Start Condition
Bus Collision During Stop Condition (Case 1) .......... 323
Bus Collision During Stop Condition (Case 2) .......... 323
Bus Collision for Transmit and Acknowledge ........... 319
Capture/Compare/PWM ........................................... 510
CLKO and I/O ........................................................... 503
Clock Synchronization .............................................. 305
Clock/Instruction Cycle ............................................... 90
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ...................... 511
Example SPI Master Mode (CKE = 1) ...................... 512
Operation.......................................................... 341
Start Condition.................................................. 321
Condition (Case 1)............................................ 322
Condition (Case 2)............................................ 322
(SCLx = 0) ........................................................ 321
(SDAx Only)...................................................... 320
(Master/Slave) .................................................. 519
(Master/Slave) .................................................. 519
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