PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 215

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PIC18F86K22-I/PTRSL

Manufacturer Part Number
PIC18F86K22-I/PTRSL
Description
MCU PIC 64K FLASH XLP 80TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3862Byte
Cpu Speed
16MIPS
No. Of Timers
11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F86K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
16.5
Timer3/5/7 can be configured to count freely or the count
can be enabled and disabled using the Timer3/5/7 gate
circuitry. This is also referred to as the Timer3/5/7 gate
count enable.
The Timer3/5/7 gate can also be driven by multiple
selectable sources.
16.5.1
The Timerx Gate Enable mode is enabled by setting
the TMRxGE bit (TxGCON<7>). The polarity of the
Timerx Gate Enable mode is configured using the
TxGPOL bit (TxGCON<6>).
FIGURE 16-2:
 2010 Microchip Technology Inc.
Timer3/5/7
TMRxGE
TxGPOL
Timer3/5/7 Gates
TxGVAL
TxG_IN
TxCKI
TIMER3/5/7 GATE COUNT ENABLE
TIMER3/5/7 GATE COUNT ENABLE MODE
N
Preliminary
N + 1
PIC18F87K22 FAMILY
When Timerx Gate Enable mode is enabled, Timer3/5/7
will increment on the rising edge of the Timer3/5/7 clock
source. When Timerx Gate Enable mode is disabled, no
incrementing will occur and Timer3/5/7 will hold the
current count. See Figure 16-2 for timing details.
TABLE 16-1:
† The clock on which TMR3/5/7 is running. For
TxCLK
more information, see TxCLK in Figure 16-1.
(†)
N + 2
(TxGCON<6>)
TxGPOL
TIMER3/5/7 GATE ENABLE
SELECTIONS
0
0
1
1
TxG Pin
N + 3
0
1
0
1
DS39960B-page 215
Counts
Holds Count
Holds Count
Counts
N + 4
Operation
Timerx

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