PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 182

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
TABLE 12-13: PORTG FUNCTIONS (CONTINUED)
TABLE 12-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
DS39960B-page 182
PORTG
TRISG
ANCON2
ODCON1
ODCON2
ODCON3
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1:
RG2/RX2/DT2/
AN18/C3INA
RG3/CCP4/AN17/
P3D/C3INB
RG4/RTCC/
T7CKI/T5G/
CCP5/AN16/
P1D/C3INC
Legend:
Pin Name
Name
2:
Unimplemented on PIC18FX5K22 devices, read as ‘0’.
Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
CCP10OD
ANSEL23
SSP1OD
Function
U2OD
Bit 7
C3INA
C3INB
C3INC
T7CKI
CCP4
RTCC
CCP5
AN18
AN17
AN16
RG2
RG3
RG4
—
—
RX2
DT2
P3D
T5G
P1D
(1)
CCP9OD
Setting
ANSEL22
CCP2OD
TRIS
U1OD
0
1
1
1
1
1
x
0
1
0
1
1
x
0
0
1
x
x
x
0
1
1
x
0
Bit 6
—
—
(1)
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ANSEL21
CCP1OD
CCP8OD
RG5
Bit 5
—
—
Type
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
(2)
Preliminary
LATG<2> data output.
PORTG<2> data input.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial data input (EUSART module); user must configure
as an input.
A/D Input Channel 18.
Default input configuration on POR. Does not affect digital output.
Comparator 3 Input A.
LATG<3> data output.
PORTG<3> data input.
CCP4 compare/PWM output. Takes priority over port data.
CCP4 capture input.
A/D Input Channel 17.
Default input configuration on POR. Does not affect digital output.
Comparator 3 Input B.
ECCP3 PWM Output D.
May be configured for tri-state during enhanced PWM.
LATG<4> data output.
PORTG<4> data input.
RTCC output.
Timer7 clock input.
Timer5 external clock gate input.
CCP5 compare/PWM output. Takes priority over port data.
CCP5 capture input.
A/D Input Channel 17.
Default input configuration on POR. Does not affect digital output.
Comparator 3 Input C.
ECCP1 PWM Output D.
May be configured for tri-state during Enhanced PWM.
ANSEL20
CCP7OD
TRISG4
Bit 4
RG4
—
—
ANSEL19
CCP6OD
TRISG3
Bit 3
RG3
—
—
Description
ANSEL18
CCP5OD
TRISG2
Bit 2
RG2
—
—
 2010 Microchip Technology Inc.
ANSEL17
CCP4OD
TRISG1
Bit 1
RG1
—
—
ANSEL16
CCP3OD
CTMUDS
SSP2OD
TRISG0
Bit 0
RG0