PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 420

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
28.3.2
The difference in the two regulators’ operation arises
with Sleep mode. The ultra low-power regulator gives
the device the lowest current in the Regulator Enabled
mode.
The on-chip regulator can go into a lower power mode
when the device goes to Sleep by setting the REGSLP
bit (WDTCON<7>). This puts the regulator in a standby
mode so that the device consumes much less current.
The on-chip regulator can also go into the Ultra Low-
Power mode, which consumes the lowest current
possible with the regulator enabled. This mode is
controlled by the RETEN bit (CONFIG1L<0>) and
SRETEN bit (WDTCON<4>).
TABLE 28-3:
DS39960B-page 420
Note 1:
Regulator
Enabled
Enabled
Enabled
Enabled
Enabled
x — Indicates that V
OPERATION OF REGULATOR IN
SLEEP
SLEEP MODE REGULATOR SETTINGS
Ultra Low-Power mode (Sleep)
Normal Operation (Sleep)
Low-Power mode (Sleep)
Normal Operation (Sleep)
Low-Power mode (Sleep)
IT
Power Mode
status is invalid.
Preliminary
WDTCON<7>
The various modes of regulator operation are shown in
Table 28-3.
When the ultra low-power regulator is in Sleep mode,
the internal reference voltages in the chip will be shut
off and any interrupts referring to the internal reference
will not wake up the device. If the BOR or LVD is
enabled, the regulator will keep the internal references
on and the lowest possible current will not be achieved.
When using the ultra low-power regulator in Sleep
mode, the device will take about 250  s typical to start
executing the code after it wakes up.
VREGSLP
(1)
0
1
0
1
x
WDTCON<4>
SRETEN
 2010 Microchip Technology Inc.
x
x
0
0
1
CONFIG1L<0>
RETEN
1
1
x
x
0