PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 118

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
EXAMPLE 7-3:
7.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
DS39960B-page 118
TBLPTRU
TBPLTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR6
PIR6
PIE6
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1:
PROGRAM_MEMORY
Name
Required
Sequence
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH
EEPGD
Bit 7
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
—
—
—
—
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PEIE/GIEL TMR0IE
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
0x55
EECON2
0xAA
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
CFGS
Bit 6
—
—
—
—
bit 21
Bit 5
—
—
—
—
(1)
Preliminary
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
INT0IE
FREE
EEIP
EEIE
Bit 4
EEIF
7.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 28.0 “Special Features of the
CPU” for more detail.
7.6
See Section 28.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
WRERR
RBIE
Bit 3
—
—
—
Flash Program Operation During
Code Protection
PROTECTION AGAINST
SPURIOUS WRITES
CMP3IP
CMP3IE
TMR0IF
CMP3IF
WREN
Bit 2
 2010 Microchip Technology Inc.
CMP2IP
CMP2IE
CMP2IF
INT0IF
Bit 1
WR
CMP1IP
CMP1IF
CMP1IE
RBIF
Bit 0
RD