PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 114

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
7.4
The erase blocks are:
• PIC18FX5K22 and PIC18FX6K22 – 32 words or
• PIC18FX7K22 – 64 words or 128 bytes
Word erase in the Flash array is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 64 or 128 bytes of program
memory is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased. The
TBLPTR<5:0> bits are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 7-2:
DS39960B-page 114
64 bytes
Required
Sequence
Erasing Flash Program Memory
ERASE_ROW
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
0x55
EECON2
0xAA
EECON2
EECON1, WR
INTCON, GIE
Preliminary
7.4.1
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
3.
4.
5.
6.
7.
; load TBLPTR with the base
; address of the memory block
; point to Flash program memory
; access Flash program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
Load the Table Pointer register with the address
of row to be erased.
Set the EECON1 register for the erase operation:
• Set the EEPGD bit to point to program memory
• Clear the CFGS bit to access program memory
• Set the WREN bit to enable writes
• Set the FREE bit to enable the erase
Disable the interrupts.
Write 0x55 to EECON2.
Write 0xAA to EECON2.
Set the WR bit.
This begins the row erase cycle.
The CPU will stall for the duration of the erase
for T
Re-enable interrupts.
IW
. (See parameter D133A.)
FLASH PROGRAM MEMORY
ERASE SEQUENCE
 2010 Microchip Technology Inc.