PIC18F86K22-I/PTRSL Microchip Technology, PIC18F86K22-I/PTRSL Datasheet - Page 237

• Manufacturer Part Number: PIC18F86K22-I/PTRSL
• Description: MCU PIC 64K FLASH XLP 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K22-I/PTRSL

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3862Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.2.4
Since the year range on the RTCC module is 2000 to
2099, the leap year calculation is determined by any year
divisible by four in the above range. Only February is
affected in a leap year.
February will have 29 days in a leap year and 28 days in
any other year.
18.2.5
All Timer registers containing a time value of seconds or
greater are writable. The user configures the time by
writing the required year, month, day, hour, minutes and
seconds to the Timer registers, via register pointers.
(See Section 18.2.8 “Register Mapping”.)
The timer uses the newly written values and proceeds
with the count from the required starting point.
The RTCC is enabled by setting the RTCEN bit
(RTCCFG<7>). If enabled while adjusting these
registers, the timer still continues to increment. However,
any time the MINSEC register is written to, both of the
timer prescalers are reset to ‘0’. This allows fraction of a
second synchronization.
The Timer registers are updated in the same cycle as
the write instruction’s execution by the CPU. The user
must ensure that when RTCEN = 1, the updated
registers will not be incremented at the same time. This
can be accomplished in several ways:
• By checking the RTCSYNC bit (RTCCFG<4>)
• By checking the preceding digits from which a
• By updating the registers immediately following
The user has visibility to the half-second field of the
counter. This value is read-only and can be reset only
by writing to the lower half of the SECONDS register.
18.2.6
The RTCSYNC bit indicates a time window during
which the RTCC clock domain registers can be safely
read and written without concern about a rollover.
When RTCSYNC = 0, the registers can be safely
accessed by the CPU.
Whether RTCSYNC = 1 or 0, the user should employ a
firmware solution to ensure that the data read did not
fall on a rollover boundary, resulting in an invalid or
partial read. This firmware solution would consist of
reading each register twice and then comparing the two
values. If the two values matched, then a rollover did
not occur.
 2010 Microchip Technology Inc.
carry can occur
the seconds pulse (or an alarm interrupt)
LEAP YEAR
GENERAL FUNCTIONALITY
SAFETY WINDOW FOR REGISTER
READS AND WRITES
Preliminary
PIC18F87K22 FAMILY
18.2.7
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RTCCFG<5>) must be set.
To avoid accidental writes to the RTCC Timer register,
it
(RTCCFG<5>) be kept clear when not writing to the
register. For the RTCWREN bit to be set, there is only
one instruction cycle time window allowed between the
55h/AA sequence and the setting of RTCWREN. For
that reason, it is recommended that users follow the
code example in Example 18-1.
EXAMPLE 18-1:
18.2.8
To limit the register interface, the RTCC Timer and
Alarm
corresponding register pointers. The RTCC Value
register window (RTCVALH and RTCVALL) uses the
RTCPTRx bits (RTCCFG<1:0>) to select the required
Timer register pair.
By reading or writing to the RTCVALH register, the
RTCC Pointer value (RTCPTR<1:0>) decrements by ‘1’
until it reaches ‘00’. When ‘00’ is reached, the
MINUTES and SECONDS value is accessible through
RTCVALH and RTCVALL until the pointer value is
manually changed.
TABLE 18-3:
The Alarm Value register windows (ALRMVALH and
ALRMVALL) use the ALRMPTR bits (ALRMCFG<1:0>)
to select the desired alarm register pair.
By reading or writing to the ALRMVALH register, the
Alarm Pointer value, ALRMPTR<1:0>, decrements by ‘1’
until it reaches ‘00’. When it reaches ‘00’, the ALRMMIN
and
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
RTCPTR<1:0>
is
movlw
movwf
movlw
movwf
bsf
ALRMSEC
00
01
10
11
recommended
Timer
WRITE LOCK
REGISTER MAPPING
registers
RTCVALH AND RTCVALL
REGISTER MAPPING
0x55
EECON2
0xAA
EECON2
RTCCFG,RTCWREN
values
RTCC Value Register Window
WEEKDAY
RTCVALH
MINUTES
SETTING THE RTCWREN
BIT
MONTH
that
—
are
are
the
accessible
accessed
DS39960B-page 237
RTCWREN
SECONDS
RTCVALL
HOURS
YEAR
DAY
through
through
bit